Serial ports. Overview. A lower-case x in a register name represents a possible value of 0, 1, or 2

9    SERIAL PORTS

Figure 9-0.

Table 9-0.

Listing 9-0.

Overview

This chapter describes the serial ports (SPORTS) available on the ADSP-2191.

In this text, the naming conventions for registers and pins use a lowercase x to represent a digit. For example, the name DTx indicates the DT0, DT1, and DT2 pins (corresponding to SPORT0, SPORT1, or SPORT2).

The ADSP-2191 has three independent, synchronous serial ports (SPORT0, SPORT1, and SPORT2) that provide an I/O interface to a wide variety of peripheral serial devices. (SPORTs provide synchronous serial data transfer only; the ADSP-2191 provides asynchronous RS-232 data transfer via the UART.) Each SPORT is a full duplex device, capable of simultaneous data transfer in both directions. Each SPORT has one group of pins (data, clock, and frame sync) for transmit and a second set of pins for receive. The receive and transmit functions are programmed separately. The SPORTs can be programmed for bit rate, frame sync, and bits per word by writing to registers in I/O space.

All three SPORTs have the same capabilities and are programmed in the same way. Each SPORT has its own set of control registers and data buffers. SPORT2 shares I/O pins with the SPI interface (SPI0 and SPI1); the SPI interface and the SPORT2 serial port cannot be enabled at the same time.

The SPORTs use frame sync pulses to indicate the beginning of each word or packet, and the bit clock marks the beginning of each data bit. External bit clock and frame sync are available for the TX and RX buffers.

With a range of clock and frame synchronization options, the SPORTs allow a variety of serial communication protocols including H.100, and provide a glueless hardware interface to many industry-standard data converters and Codecs.

The SPORTs can operate at up to 1/2 the full clock rate of HCLK, providing each with a maximum data rate of CCLK/2 Mbit/s in 1:1 (CCLK:HCLK) clock mode (where CCLK is the DSP core clock, and HCLK is the peripheral clock). Independent transmit and receive functions provide greater flexibility for serial communications. SPORT data can be automatically transferred to and from on-chip memory using DMA block transfers. Additionally, each of the SPORTs offers a TDM (time division multiplexed) multichannel mode.

SPORT clocks and frame syncs can be internally generated by the DSP or received from an external source. The SPORTs can operate with little-endian or big-endian transmission formats, with word lengths selectable from 3 to 16 bits. They offer selectable transmit modes and optional µ-law or A-law companding in hardware.

Each of the SPORTs offers the following features and capabilities:

•  Provides independent transmit and receive functions

•  Transfers serial data words from three to sixteen bits in length, either MSB-first or LSB-first

•  Double-buffers data (both receive and transmit functions have a data buffer register and a shift register), providing additional time to service the SPORT

•  Compands—can perform A-law and µ-law hardware companding