System interface. Overview. Pin Descriptions. Pin Descriptions for 128-LQFP Package Processors. Pin Descriptions for 100-LQFP Package Processors

Write to PFDATA sets pin value and may cause interrupt

(level- or edge-sensitive)

•  Read of PFDATA gives set value

After reset, the PF pins default to inputs and the interrupts are disabled by the IMASK register’s default value. The pins can be used as PF outputs by changing the PFTYPE register and leaving the interrupt disabled in IMASK. If the pins are to be used as interrupts, then the PFTYPE register need not be changed, but the interrupt must be enabled in the IMASK register.

Common-Mode Pins

Table 7-3 provides a description of the pins that are common to both Full Memory Mode and Host Memory Mode in 100-LQFP packages. In cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics. All pin descriptions also apply to the processors in 144-Ball Mini-BGA packages unless otherwise noted.

Table 7-3. Common-Mode Pins

Table 7-3. Common-Mode Pins (Cont’d)

Table 7-3. Common-Mode Pins (Cont’d)

Table 7-3. Common-Mode Pins (Cont’d)

1  Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag.

2  SPORT configuration determined by the DSP System Control register. Software configurable.

Memory Mode Pins

Table 7-4 provides a description of Full Memory Mode pins and Table 7-5 provides a description of the Host Memory Mode pins on ADSP-218x processors in 100-lead LQFP and 144-MBGA packages.

Table 7-4. Full Memory Mode Pins (Mode C = 0)

Table 7-5. Host Memory Mode Pins (Mode C = 1)

1  In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS,

DMS, and IOMS signals.

Active or Passive Mode Pin Configuration

To decrease the package size of the ADSP-218x family processors for the 100-LQFP packages, the IDMA bus and associated control signals are multiplexed with the external Address and Data busses. The logic value of the Mode pins are latched on the rising edge of the RESET signal. The values of the Mode pins determine whether the DSP will boot from an EPROM or be booted from an external host processor.

The Mode pins also determine whether the DSP’s external pins are used for IDMA accesses (Host Memory mode) or whether the full 14-bit address bus and 24-bit data bus is active (Full Memory mode).

The Mode pins can be set for active or passive configuration. An active configuration means that the Mode pin is used as a Mode pin during reset, but also functions alternately as a Programmable Flag pin or Interrupt Signal during runtime. Passive configuration means that the Mode pin is used only as a Mode pin and has no alternate function during runtime.

A passive configuration is more easily implemented because only a simple pullup or pulldown resistor is needed to maintain a proper logic level for the Mode pin. (Tying a Mode pin directly to V_DD or GND is also acceptable.)

An Active configuration requires either a weak pullup or pulldown (on the order of 100 kΩ) or some type of tristate driver or logic gate to allow for proper operation of the pin during its alternate mode of functioning as a Programmable Flag pin or Interrupt signal. (A weak pullup or pulldown resistor is used to reduce the amount of current flow to the input pin of the DSP and to minimize the amount of current going through an output driver.) For more information on setting the Mode pins for an active or passive configuration, please see “Using Mode Pins with RESET and ERESET Signals” on page 7-64.

Terminating Unused Pins

Table 7-6 shows the recommendations for terminating unused pins. Additional recommendations follow the table.

Table 7-6 shows the multiplexed pins for the Host Memory mode