do: out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
component kr580vv55 is
port (
pa: inout STD_LOGIC_VECTOR (7 downto 0);
pb: inout STD_LOGIC_VECTOR (7 downto 0);
pc: inout STD_LOGIC_VECTOR (7 downto 0);
pd: inout STD_LOGIC_VECTOR (7 downto 0);
cs: in STD_LOGIC;
rd: in STD_LOGIC;
wr: in STD_LOGIC;
a1: in STD_LOGIC;
a0: in STD_LOGIC
);
end component;
signal one, zero:STD_LOGIC;
signal ol1, ol2, ol3,ol4, ol5, ol6, ol7, ol8, ol9, ol10,ol11,ol12,ol13,ol14,ol15,
ol16,ol17,ol18,ol19,ol20,ol21,ol22,ol23,ol24,ol25,ol26,ol27,ol28,ol29:STD_LOGIC;
begin
one<='1';
zero<='0';
D1: k589ap26
port map db(0)=>vh0,db(1)=>vh1,db(2)=>vh2,db(3)=>vh3,bs=>vh8,cs=>vh10,do(0)=>ol1,
do(1)=>ol2,do(2)=>ol3,do(3)=>ol4,di(0)=>ol1,di(1)=>ol2,di(2)=>ol3,di(3)=>ol4);
D2: k589ap26
port map (db(0)=>vh4,db(1)=>vh5,db(2)=>vh6,db(3)=>vh7,bs=>vh8,cs=>vh10,do(0)=>ol5,
do(1)=>ol6,do(2)=>ol7,do(3)=>ol8,di(0)=>ol5,di(1)=>ol6,di(2)=>ol7,di(3)=>ol8);
D3:k559ip2p
port map (k1=>vh11,l1=>vh11,k2=>vh12,l2=>vh12,k3=>vh13,l3=>vh13,k4=>vh14,
l4=>vh14, m1=>ol9,m2=>ol10,m3=>ol11,m4=>ol12);
D4:k559ip2p
port map (k1=>vh15,l1=>vh15,k2=>vh16,l2=>vh16,k3=>vh17,l3=>vh17,k4=>vh18,
l4=>vh18, m1=>ol13,m2=>ol14,m3=>ol15,m4=>ol16);
D5:d56
port map (q1=>ol11,q2=>one,q3=>ol17);
D6:d56
port map (q1=>ol12,q2=>one,q3=>ol18);
D7:d56
port map (q1=>ol13,q2=>one,q3=>ol19);
D8:d56
port map (q1=>ol14,q2=>one,q3=>ol20);
D9:d56
port map (q1=>ol15,q2=>one,q3=>ol21);
D10:d56
port map (q1=>ol16,q2=>one,q3=>ol22);
D11:kr580vv55
port map (pd(0)=>ol1, pd(1)=>ol2, pd(2)=>ol3, pd(3)=>ol4, pd(4)=>ol5,
pd(5)=>ol6,pd(6)=>ol7, pd(7)=>ol8, a0=>ol9, a1=>ol10, wr=>ol27, rd=>ol26,
cs=>vh10,pa(0)=>vd0,pa(1)=>vd1,pa(2)=>vd2,pa(3)=>vd3,pa(4)=>vd4,pa(5)=>vd5,
pa(6)=>vd6,pa(7)=>vd7,
pb(0)=>vd8,pb(1)=>vd9,pb(2)=>vd10,pb(3)=>vd11,pb(4)=>vd12,pb(5)=>vd13,
pb(6)=>vd14,pb(7)=>vd15,
pc(0)=>vd16,pc(1)=>vd17,pc(2)=>vd18,pc(3)=>vd19,pc(4)=>vd20,pc(5)=>vd21,
pc(6)=>vd22,pc(7)=>vd23);
D12:k559ip2p
port map (k1=>vh8,l1=>vh10,k2=>vh10,l2=>vh9,k3=>zero,l3=>zero,k4=>zero,l4=>zero,
m1=>ol23,m2=>ol24,m3=>one,m4=>one);
D13:k155la2
port map (A=> one,B=> one,C=>ol17,D=>ol18,E=>ol19,F=>ol20,H=>ol22 ,G=> ol21,
Y=>ol25);
D14:k155la3
port map (f1=>ol23, v1=>ol23, z1=>ol26, f2=>ol24, v2=>ol24, z2=>ol27, f3=>one, f4=>one,v3=>one, v4=>one, z3=>zero, z4=>zero);
D15:k155la8
port map (t1=>ol28, e1=>ol28, w1=>ol29, t2=>one, t3=>one, t4=>one, e2=>one, e3=>one,
e4=>one, w2=>zero, w3=>zero, w4=>zero );
end structure;
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