Логический элемент «И-НЕ» К155ЛЕ1. Логический элемент «НЕ» К155ЛН1. Дешифратор-демультиплексор К155ИЕ7, страница 3

a_out_bus: out STD_LOGIC_VECTOR (6 downto 0);

ras_inv: inout STD_LOGIC;

cas_inv_bus: out STD_LOGIC_VECTOR (3 downto 0);

we_inv_bus: out STD_LOGIC_VECTOR (3 downto 0)

);

end top;

architecture top of top is

component k155ln1 is

port (

input: in STD_LOGIC;

output_inv: out STD_LOGIC

);

end component;

component k155ie7 is

port (

d: in STD_LOGIC_VECTOR (3 downto 0);

pe_inv: in STD_LOGIC;

r: in STD_LOGIC;

cu: in STD_LOGIC;

cd: in STD_LOGIC;

q: out STD_LOGIC_VECTOR (3 downto 0);

tcu_inv: out STD_LOGIC;

tcd_inv: out STD_LOGIC

);

end component;

component k155tm2 is

port (

r_inv: in STD_LOGIC;

d: in STD_LOGIC;

c: in STD_LOGIC;

s_inv: in STD_LOGIC;

q: out STD_LOGIC;

q_inv: out STD_LOGIC

);

end component;

component k155id4 is

port (

a1: in STD_LOGIC;

a0: in STD_LOGIC;

ea1: in STD_LOGIC;

ea2_inv: in STD_LOGIC;

eb1_inv: in STD_LOGIC;

eb2_inv: in STD_LOGIC;

e_inv: out STD_LOGIC_VECTOR(8 downto 1)

);

end component;

component k155le1 is

port (

input1: in STD_LOGIC;

input2: in STD_LOGIC;

output_inv: out STD_LOGIC

);

end component;

component k155kp2 is

port (

i: in STD_LOGIC_VECTOR (4 downto 1);

s1: in STD_LOGIC;

s0: in STD_LOGIC;

e_inv: in STD_LOGIC;

y: out STD_LOGIC

);

end component;

signal a_in_bus_int:STD_LOGIC_VECTOR (23 downto 1);

signal bus1:STD_LOGIC_VECTOR(8 downto 1);

signal d3_in_bus:STD_LOGIC_VECTOR (3 downto 0);

signal d3_out_bus:STD_LOGIC_VECTOR (3 downto 0);

signal d81_in_bus:STD_LOGIC_VECTOR (3 downto 0);

signal d82_in_bus:STD_LOGIC_VECTOR (3 downto 0);

signal d91_in_bus:STD_LOGIC_VECTOR (3 downto 0);

signal d92_in_bus:STD_LOGIC_VECTOR (3 downto 0);

signal d101_in_bus:STD_LOGIC_VECTOR (3 downto 0);

signal d102_in_bus:STD_LOGIC_VECTOR (3 downto 0);

signal d111_in_bus:STD_LOGIC_VECTOR (3 downto 0);

signal zero,one:STD_LOGIC;

signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13:STD_LOGIC;

begin

zero<='0';

one<='0';

a_in_bus_int(16 downto 1)<=a_in_bus;

d11:k155le1 port map (input1=>memr_inv,

input2=>blk,

output_inv=>s1);

d12:k155le1 port map (input1=>blk,

input2=>memw_inv,

output_inv=>s2);

d13:k155le1 port map (input1=>s1,

input2=>s2,

output_inv=>s3);

d53:k155ln1 port map (input=>s3,

output_inv=>s4);

d61:k155tm2 port map (r_inv=>s4,

c=>ttl,

d=>s5,

s_inv=>'X',

q=>s6,

q_inv=>s5);

d54:k155ln1 port map (input=>s5,

output_inv=>s7);

d55:k155ln1 port map (input=>s7,

output_inv=>s8);

d2:k155ie7 port map (d=>a_in_bus_int(20 downto 17),

cu=>ttl,

cd=>'X',

pe_inv=>s8,

r=>zero,

q=>a_in_bus_int(20 downto 17),

tcu_inv=>s9);

d3_in_bus<=s10&a_in_bus_int(23 downto 21);

d3:k155ie7 port map (d=>d3_in_bus,

cu=>s9,

cd=>'X',

pe_inv=>s8,

r=>zero,

q=>d3_out_bus);

a_in_bus_int(23 downto 21)<=d3_out_bus(2 downto 0);                      

d14:k155le1 port map (input1=>ttl,

input2=>s5,

output_inv=>s11);

d56:k155ln1 port map (input=>s2,

output_inv=>s12);

d7:k155id4 port map (eb1_inv=>s5,

eb2_inv=>ttl,

a0=>a_in_bus_int(15),

a1=>a_in_bus_int(16),

ea1=>s11,

ea2_inv=>s12,

e_inv=>bus1);

d51:k155ln1 port map (input=>ttl,

output_inv=>ras_inv);

d52:k155ln1 port map (input=>ras_inv,

output_inv=>s13);

d81_in_bus<=a_in_bus_int(8)&a_in_bus_int(1)&a_in_bus_int(17)&a_in_bus_int(17);

d81:k155kp2 port map (i=>d81_in_bus,

e_inv=>zero,

s0=>s6,

s1=>s13,

y=>a_out_bus(0));

d82_in_bus<=a_in_bus_int(9)&a_in_bus_int(2)&a_in_bus_int(18)&a_in_bus_int(18);

d82:k155kp2 port map (i=>d82_in_bus,

e_inv=>zero,

s0=>s6,

s1=>s13,

y=>a_out_bus(1));

d91_in_bus<=a_in_bus_int(10)&a_in_bus_int(3)&a_in_bus_int(19)&a_in_bus_int(19);

d91:k155kp2 port map (i=>d91_in_bus,

e_inv=>zero,

s0=>s6,

s1=>s13,

y=>a_out_bus(2));

d92_in_bus<=a_in_bus_int(11)&a_in_bus_int(4)&a_in_bus_int(20)&a_in_bus_int(20);

d92:k155kp2 port map (i=>d92_in_bus,

e_inv=>zero,

s0=>s6,

s1=>s13,

y=>a_out_bus(3));

d101_in_bus<=a_in_bus_int(12)&a_in_bus_int(5)&a_in_bus_int(21)&a_in_bus_int(21);

d101:k155kp2 port map (i=>d101_in_bus,

e_inv=>zero,

s0=>s6,

s1=>s13,

y=>a_out_bus(4));

d102_in_bus<=a_in_bus_int(13)&a_in_bus_int(6)&a_in_bus_int(22)&a_in_bus_int(22);

d102:k155kp2 port map (i=>d102_in_bus,

e_inv=>zero,

s0=>s6,

s1=>s13,

y=>a_out_bus(5));

d111_in_bus<=a_in_bus_int(14)&a_in_bus_int(7)&a_in_bus_int(23)&a_in_bus_int(23);

d111:k155kp2 port map (i=>d111_in_bus,

e_inv=>zero,

s0=>s6,

s1=>s13,

y=>a_out_bus(6));

cas_inv_bus<=bus1(4 downto 1);

we_inv_bus<=bus1(8 downto 5);

-- <<enter your statements here>>

end top;

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