Логический элемент «И-НЕ» К155ЛЕ1. Логический элемент «НЕ» К155ЛН1. Дешифратор-демультиплексор К155ИЕ7, страница 2

Y – выход

Задержка – 63нс

Принцип действия

При наличие низкого разрешающего уровня на E, сигнал с линии с номером соответствующим числу S0..1 передается на выход Y.

Waveform

Приложение

Код VHDL

k155ln1.VHD

library IEEE;

use IEEE.std_logic_1164.all;

entity k155ln1 is

port (

input: in STD_LOGIC;

output_inv: out STD_LOGIC

);

end k155ln1;

architecture k155ln1 of k155ln1 is

begin

output_inv<=transport not input after 27ns;

-- <<enter your statements here>>

end k155ln1;

k155ie7.VHD

library IEEE;

use IEEE.std_logic_1164.all;

entity k155ie7 is

port (

d: in STD_LOGIC_VECTOR (3 downto 0);

pe_inv: in STD_LOGIC;

r: in STD_LOGIC;

cu: in STD_LOGIC;

cd: in STD_LOGIC;

q: out STD_LOGIC_VECTOR (3 downto 0);

tcu_inv: out STD_LOGIC;

tcd_inv: out STD_LOGIC

);

end k155ie7;

architecture k155ie7 of k155ie7 is

begin

process (d,pe_inv,r,cu,cd)

variable d_int,tmp:integer;

variable q_int:STD_LOGIC_VECTOR(3 downto 0);

variable tcu_inv_int,tcd_inv_int:STD_LOGIC;

begin

if (cu='0' and cu'event) or (cd='0' and cd'event) then

tcu_inv_int:='1';

tcd_inv_int:='1';

end if;

if r='0' and pe_inv='1' and cu='1' and cu'event then

d_int:=d_int+1;

if d_int=16 then

d_int:=0;

tcu_inv_int:='0';

end if;

end if;

if r='0' and pe_inv='1' and cd='1' and cd'event then

d_int:=d_int-1;

if d_int=-1 then

d_int:=15;

tcu_inv_int:='0';

end if;

end if;

tmp:=d_int;

q_int:="0000";

if tmp>=8 then

tmp:=tmp-8;

q_int(3):='1';

end if;

if tmp>=4 then

tmp:=tmp-4;

q_int(2):='1';

end if;

if tmp>=2 then

tmp:=tmp-2;

q_int(1):='1';

end if;

if tmp=1 then

q_int(0):='1';

end if;

if r='0' and pe_inv='0' then

q_int:=d;

tcd_inv_int:=cd;

tcu_inv_int:=cu;

end if;

if r='1' and cd='0' then

d_int:=0;

q_int:="0000";

tcu_inv_int:='1';

tcd_inv_int:='0';

elsif r='1' and cd='1' then

q_int:="0000";

tcu_inv_int:='1';

tcd_inv_int:='1';

end if;

q<=transport q_int after 32ns;

tcu_inv<=transport tcu_inv_int after 32ns;

tcd_inv<=transport tcd_inv_int after 32ns;

end process;

-- <<enter your statements here>>

end k155ie7;

k155tm2.VHD

library IEEE;

use IEEE.std_logic_1164.all;

entity k155tm2 is

port (

r_inv: in STD_LOGIC;

d: in STD_LOGIC;

c: in STD_LOGIC;

s_inv: in STD_LOGIC;

q: out STD_LOGIC;

q_inv: out STD_LOGIC

);

end k155tm2;

architecture k155tm2 of k155tm2 is

begin

process (r_inv,d,c,s_inv)

variable state,state_inv:STD_LOGIC;

begin

if c='1' and c'event then

state:=d;

state_inv:=not state;

end if;

if r_inv='0' and s_inv='1' then

state:='0';

state_inv:='1';

end if;

if r_inv='1' and s_inv='0' then

state:='1';

state_inv:='0';

end if;

if r_inv='0' and s_inv='0' then

state:='1';

state_inv:='1';

end if;

q<=transport state after 30ns;

q_inv<=transport state_inv after 30ns;

end process;

-- <<enter your statements here>>

end k155tm2;

k155id4.VHD

library IEEE;

use IEEE.std_logic_1164.all;

entity k155id4 is

port (

a1: in STD_LOGIC;

a0: in STD_LOGIC;

ea1: in STD_LOGIC;

ea2_inv: in STD_LOGIC;

eb1_inv: in STD_LOGIC;

eb2_inv: in STD_LOGIC;

e_inv: out STD_LOGIC_VECTOR(8 downto 1)

);

end k155id4;

architecture k155id4 of k155id4 is

begin

process (a1,a0,ea1,ea2_inv,eb1_inv,eb2_inv)

variable ind:integer;

variable e_inv_int:STD_LOGIC_VECTOR(8 downto 1);

begin

ind:=0;

if a0='1' then

ind:=ind+1;

end if;

if a1='1' then

ind:=ind+2;

end if;

e_inv_int:="11111111";

e_inv_int(ind+1):=not (ea1 and not ea2_inv);

e_inv_int(ind+5):=not (not eb1_inv and not eb2_inv);

e_inv<=transport e_inv_int after 32ns;

end process;

-- <<enter your statements here>>

end k155id4;

k155le1.VHD

library IEEE;

use IEEE.std_logic_1164.all;

entity k155le1 is

port (

input1: in STD_LOGIC;

input2: in STD_LOGIC;

output_inv: out STD_LOGIC

);

end k155le1;

architecture k155le1 of k155le1 is

begin

output_inv<= transport not (input1 or input2) after 15ns;

-- <<enter your statements here>>

end k155le1;

k155kp2.VHD

library IEEE;

use IEEE.std_logic_1164.all;

entity k155kp2 is

port (

i: in STD_LOGIC_VECTOR (4 downto 1);

s1: in STD_LOGIC;

s0: in STD_LOGIC;

e_inv: in STD_LOGIC;

y: out STD_LOGIC

);

end k155kp2;

architecture k155kp2 of k155kp2 is

begin

process (i,s1,s0,e_inv)

variable ind:integer;

begin

if e_inv='0' then

ind:=0;

if s0='1' then

ind:=ind+1;

end if;

if s1='1' then

ind:=ind+2;

end if;

y<=transport i(ind+1) after 63ns;

else

y<=transport '0' after 63ns;

end if;

end process;

-- <<enter your statements here>>

end k155kp2;

top.vhd

library IEEE;

use IEEE.std_logic_1164.all;

entity top is

port (

a_in_bus: in STD_LOGIC_VECTOR (15 downto 0);

memr_inv: in STD_LOGIC;

blk: in STD_LOGIC;

memw_inv: in STD_LOGIC;

ttl: in STD_LOGIC;