Digital Transmitter of Phase Modulated Signals Based on DSP. Robert Kotrys, Piotr Remlein and Pawel Szulakiewicz, страница 2

The scrambled data stream to be transmitted is divided into groups of 4 data bits. The first two bits in time are first differentially encoded into Y1_N and Y2_N. The two differentially encoded bits are used as input to a systematic convolutional encoder which generates a redundant bit Y0_N. This redundant bit and the 4 information-caring bits

Y1_N, Y2_N, Y3_N  and Y4_N are then mapped into coordinates of the signal element to be transmitted.

CONTROL AD7008 - ASSEMBLER SOLUTION

The 32 point constellation are used in v.32 transmitter. Is not necessary to change the frequency, but we have to modify both phase and amplitude. It’s achieved by modify Phase Register and IQMod Registers in AD7008. The simplest way is a Look Up Table with a proper mapper value. We need only 21 processor cycle to generate each symbol point. The point generation time is independ from constellation size. NCO AD7008 control routine is shown bellow.

.MODULE/RAM 32QAM_SUB;

.ENTRY mod;

.VAR/DM/RAM tabsyn[32];   {I LUT}

.VAR/DM/RAM tabqua[32];   {Q LUT}

.VAR/DM/RAM s_ster;{AD7008 controll}

.VAR/DM/RAM s_mod; {AD7008 data} .VAR/DM/RAM symb; {symbol source} mod: AY1=0;

AX0=DM(symb);

AY0=0x001F; AR=AX0 AND AY0;	{mask symbol bits}
L1=0; L2=0; I1=^tabsyn; I2=^tabgua; M1=AR; M2=AR; M0=0; MODIFY(I1,M1); MODIFY(I2,M2);	{initialisation}
AX0=DM(I1,M0); RESET FL1; DM(s_mod)=AX0;	{read I from LUT}
AX0=DM(I2,M0); DM(s_mod)=AX0;	{read Q from LUT}
AX0=11;	{AD78008 control}

DM(s_ster)=AX0;

SET FL1;

RTS;

.ENDMOD;

CONCLUSION

The complete cost of encoding  one symbol (without scrambling) is 57 cycle, additional 21 cycle is need for mapping constellation point with NCO. The most time consuming is convolutionnal encoding 42 cycle. With 60 ns machine cycle, the time to complete one symbol is about 4.7 µs. In compare to V.32 modulation rate, it’s only 0.88% of symbol period.

The main advantages of the described transmitter are a compact hardware with possibility to make each modulation scheme. The signals are modulated direct at intermediate frequency with full digital quality and stability. Modulation have small part in computation time. The processor has a lot of time to do another task as demodulation, decoding and  etc.

REFERENCES

[1]  "AD 7008 technical reference."; Analog Devices 1993.

[2]  "ADSP 2100 Family User's Manual."; Analog Devices 1993.

[3]  ITU-T Recommendation V.32;

[4]  Biglieri E., Divsalar D., McLine P. J., Simmon M. K., "Introdution to Trellis-Code Modulation with Applications."; MPC New York, 1991.

[5]  Pietribon S., D. Costello, A. Lafanerche,G. Ungerbeock, D. Costello: "Trellis-coded multidimensional phase modulation" IEEE trans., 1990, TI-36, str. 63-89.

[6]  Szulakiewicz P., Kotrys R.: "New TCM codes for 4PSK-2PSK modulation", Electronics Letters 32rd, June 1994, Vol. 30 No. 13 str. 1032-1033.

[7]  Ungerboeck G., "Chanel coding with multilevel-phase signals." IEEE Trans. Inf. Theory, vol. IT-28, pp. 55-67, Jan. 1982.

[8]  Cavers J., Moss B., Stapleton S.; "Amultistage DSP-based quadrature modulator.", Canadian Conference on Electrical and Computer Enginering. Quebec, Sept. 25-27 1991.

[9]  Kotrys R., Szulakiewicz P.; „A Digital Transmitter of CPM signals” IFIP TC6 Personal Wriless Communications, pros.

pp. 87-95, 25-25 April 1995.

APPENDIX

Bellow we described an assembler routine of differential and convolutional encoder.

{---Differential encoder---}

{ input bits: ax0 -> 000X where X is input bits Q1-Q4 }

code:i3 =^t_table;

{output bits LUT address} ay0 = h#000C;

{bits mask Q1 Q2} ar = ax0 and ay0; ay1= dm(last_ys);

{output bits in previous symbol Y1

Y2}

ar = ar xor ay1;

{bits Q1 Q2 Y1 Y2 are in ar} m3 = ar;

{addtees in t_table} modify(I3,M3);

{for Y1 Y2}

si = dm(i3,m0);

{bits from table on encoder output}

dm(last_ys) = si; ay1 = 3; af = ax0 and ay1;

{mask Q3 Q4} sr = lshift si by 2(lo); ar = sr0 + af;

{ar ->Y1 Y2 Q3 Q4} dm(diff_out) = ar;

{save the encoded symbol} rts;

{******** convolutional encoding ******} {input Y1 Y2 Q3 Q4 as "diff_out"

LSB, output are encoded Y0 Y1 Y2 } c_code:sr0 = 0;

{register reset srx} sr1 = 0;

{for bits Y1 and Y2 } si = dm(diff_out);

{get input bits} se = -3; sr = lshift si by -3(hi);

{shift Y1 to LSB} ay0 = 1; ar = sr1 and ay0;

{evaluate Y1}

dm(Y1) = ar;

{save bit Y1} ax0 = ar; sr = lshift si by -2(HI);

{shift Y2 to LSB} ar = sr1 and ay0;

{ evaluate Y2} dm(Y2) = ar;

{save bit Y2} ay0 = ar; ar = ax0 XOR ay0;

{Y2 xor Y1} ay1 = dm(delay_val_3); ar = ar xor ay1;

{Y2 xor Y1 xor D3} dm(intermed_1) = ar;

{save previous value} ax0 = dm(delay_val_2); ar = ax0 XOR ay0; { Y2 xor D2} dm(intermed_2) = ar;

{save intermediate value} ay0 = dm(delay_val_1); dm(delay_val_3) = ay0;

{evaluate D3 D3=D1} ar = ar and ay0;

{AND2 (Y2 xor D2) and D1} ay1 = dm(intermed_1); ar = ar XOR ay1;

{evaluate D2} dm(delay_val_1) = ar;

{save D2} ax1 = dm(Y1); ar = ax1 and ay0;

{ AND1 Y1and D1} ay0 = dm(intermed_2); ar = ar xor ay0;

{evaluate D1} dm(delay_val_2) = ar;

{save D1} dm(Y0) = ar;

{evaluate redundant bit } call form;

rts;