Проектирование специализированного микроконтроллера (Приложение к курсовой работе по дисциплине «Технические средства микропроцессорных систем»), страница 2

    elsif ready = '1' then

      a <= tmp & c(510 downto 0) & '0';

      start <= '1';

    else

      start <= '0';

    end if;

  end if;

end process;

end architecture;

Исходный текст файла « test_gen_n.vhd »

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity test is

end test;

architecture test_gen_n of test is

component gen_n

  port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        prime_in: IN std_logic_VECTOR(511 downto 0);

        empty : in std_logic;

        rd_ack : in std_logic;

        rd_en : out std_logic;

        out_valid : out std_logic;

        fi_out: OUT std_logic_VECTOR(1023 downto 0);

        n_out: OUT std_logic_VECTOR(1023 downto 0));

end component;

signal clk : std_logic := '0';

signal reset_l : std_logic := '0';

signal prime_in: std_logic_vector(511 downto 0);

signal fi_out, n_out: std_logic_vector(1023 downto 0);

signal out_valid : std_logic;

signal start, ready, rd_en, rd_ack, empty : std_logic;

signal count_i :integer;

constant c: std_logic_vector(511 downto 0) := (others => '0');

begin

clk <= not clk after 5 ns;

reset_l <= '1' after 20 ns;

my_gen_n : gen_n port map (clk, reset_l, start, ready, prime_in, empty, rd_ack, rd_en, out_valid, fi_out, n_out);

process(clk)

variable count:integer;

begin

  if clk'event and clk = '1' then

    count_i <= count;

    rd_ack <= '0';

    count := count + 1;

    start <= '0';

    if reset_l = '0' then

      start <= '0';

      prime_in <= (others => '0');

      rd_ack <= '0';

      empty <= '1';

      count := 0;

    elsif ready = '1' and count = 3 then

      start <= '1';

    elsif count = 10 then

      empty <= '0';

    elsif rd_en = '1'and count < 20 then

      rd_ack <= '1';

      prime_in <= "11"  & c(509 downto 3) & "101";

      empty <= '1';

    elsif count = 20 then

      empty <= '0';

    elsif rd_en = '1' then

      rd_ack <= '1';

      prime_in <= "1101"  & c(507 downto 0) ;

      empty <= '1';

    end if;

  end if;

end process;

end architecture;

Исходный текст файла « test_mod_mul_1024.vhd »

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity test is

end test;

architecture test_add_sub of test is

component mod_mult_1024

  port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        B: IN std_logic_VECTOR(1023 downto 0);

        N: IN std_logic_VECTOR(1023 downto 0);

        M_valid : out std_logic;

        M: OUT std_logic_VECTOR(1023 downto 0));

end component;

signal clk : std_logic := '0';

signal reset_l : std_logic := '0';

signal a,b,m,n: std_logic_vector(1023 downto 0);

signal m_valid : std_logic;

signal start, ready : std_logic;

signal d: std_logic_vector(1023 downto 0);

constant c: std_logic_vector(1023 downto 0) := (others => '1');

begin

clk <= not clk after 5 ns;

reset_l <= '1' after 20 ns;

my_mod_mult : mod_mult_1024 port map (clk, reset_l, start, ready, a, b, n, m_valid, m);

process(clk)

begin

  if clk'event and clk = '1' then

    if reset_l = '0' then

      b <= (others => '0');

      a <= (others => '0');

      n <= (others => '0');

      d <= x"8" & x"0000" & c(1003 downto 0);

    elsif ready = '1' then

      start <= '1';