Другие предметы \ Математическое моделирование и автоматизированное проектирование технических систем

Проектирование и моделирование схем комбинационной логики в пакете ActiveHDL, страница 2

Time delta X1 X2 X3 X4 Y1 Y2

0.000 0 0 0 0 0 U U

0.000 1 0 0 0 0 0 1

50.000 ns 0 1 0 0 0 0 1

50.000 ns 1 1 0 0 0 0 0

100.000 ns 0 0 1 0 0 0 0

100.000 ns 1 0 1 0 0 0 1

150.000 ns 0 1 1 0 0 0 1

150.000 ns 1 1 1 0 0 1 1

200.000 ns 0 0 0 1 0 1 1

250.000 ns 0 1 0 1 0 1 1

300.000 ns 0 0 1 1 0 1 1

350.000 ns 0 1 1 1 0 1 1

400.000 ns 0 0 0 0 1 1 1

400.000 ns 1 0 0 0 1 0 0

450.000 ns 0 1 0 0 1 0 0

500.000 ns 0 0 1 0 1 0 0

500.000 ns 1 0 1 0 1 0 1

550.000 ns 0 1 1 0 1 0 1

550.000 ns 1 1 1 0 1 1 1

600.000 ns 0 0 0 1 1 1 1

600.000 ns 1 0 0 1 1 1 0

650.000 ns 0 1 0 1 1 1 0

700.000 ns 0 0 1 1 1 1 0

700.000 ns 1 0 1 1 1 1 1

750.000 ns 0 1 1 1 1 1 1

800.000 ns 0 0 0 0 0 1 1

800.000 ns 1 0 0 0 0 0 1

850.000 ns 0 1 0 0 0 0 1

850.000 ns 1 1 0 0 0 0 0

900.000 ns 0 0 1 0 0 0 0

900.000 ns 1 0 1 0 0 0 1

950.000 ns 0 1 1 0 0 0 1

950.000 ns 1 1 1 0 0 1 1

1.000 us 0 0 0 1 0 1 1

Time delta X1 X2 X3 X4 Y1 Y2

0.000 2 0 0 0 0 0 U

0.000 4 0 0 0 0 0 1

50.000 ns 0 1 0 0 0 0 1

50.000 ns 4 1 0 0 0 0 0

100.000 ns 0 0 1 0 0 0 0

100.000 ns 1 0 1 0 0 0 1

150.000 ns 0 1 1 0 0 0 1

150.000 ns 2 1 1 0 0 1 1

200.000 ns 0 0 0 1 0 1 1

200.000 ns 1 0 0 1 0 1 0

200.000 ns 4 0 0 1 0 1 1

250.000 ns 0 1 0 1 0 1 1

300.000 ns 0 0 1 1 0 1 1

350.000 ns 0 1 1 1 0 1 1

400.000 ns 0 0 0 0 1 1 1

400.000 ns 2 0 0 0 1 0 1

400.000 ns 3 0 0 0 1 0 0

450.000 ns 0 1 0 0 1 0 0

500.000 ns 0 0 1 0 1 0 0

500.000 ns 1 0 1 0 1 0 1

550.000 ns 0 1 1 0 1 0 1

550.000 ns 2 1 1 0 1 1 1

600.000 ns 0 0 0 1 1 1 1

600.000 ns 1 0 0 1 1 1 0

650.000 ns 0 1 0 1 1 1 0

700.000 ns 0 0 1 1 1 1 0

700.000 ns 1 0 1 1 1 1 1

750.000 ns 0 1 1 1 1 1 1

800.000 ns 0 0 0 0 0 1 1

800.000 ns 1 0 0 0 0 1 0

800.000 ns 2 0 0 0 0 0 0

800.000 ns 3 0 0 0 0 0 1

850.000 ns 0 1 0 0 0 0 1

850.000 ns 4 1 0 0 0 0 0

900.000 ns 0 0 1 0 0 0 0

900.000 ns 1 0 1 0 0 0 1

950.000 ns 0 1 1 0 0 0 1

950.000 ns 2 1 1 0 0 1 1

1.000 us 0 0 0 1 0 1 1

1.000 us 1 0 0 1 0 1 0

1.000 us 4 0 0 1 0 1 1

7. Дополнительное задание

x1 x2 x3 x4

y1 y2 y3

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 0

0 1 1

0 0 0

0 1 0

0 1 1

0 0 0

0 1 0

0 1 1

0 0 0

0 1 1

1 0 0

0 0 1

1 1 0

library IEEE;

use IEEE.std_logic_1164.all;

entity nLab_9_ext_device is

port(X:in std_logic_vector(1 to 4);

Y:out std_logic_vector(1 to 3));

end;

architecture nLab_9_ext_arch of nLab_9_ext_device is

type input_array is array(0 to 15) of std_logic_vector(1 to 4);

type output_array is array(0 to 15) of std_logic_vector(1 to 3);

constant x_s:input_array:=("0000","0001","0010","0011","0100","0101","0110","0111","1000","1001","1010","1011","1100","1101","1110","1111");

constant y_s:output_array:=("000","011","011","011","000",

"010","011","000","010","011","000","011","011","100","001","110");

begin

process (X)

begin

y<="000";

for i in 0 to 15 loop

if (x=x_s(i)) then

y<=y_s(i);

end if;

end loop;

end process;

end;

Time delta X Y

0.000 0 0 U

0.000 1 0 0

10.000 ns 0 1 0

10.000 ns 1 1 3

20.000 ns 0 2 3

30.000 ns 0 3 3

40.000 ns 0 4 3

40.000 ns 1 4 0

50.000 ns 0 5 0

50.000 ns 1 5 2

60.000 ns 0 6 2

60.000 ns 1 6 3

70.000 ns 0 7 3

70.000 ns 1 7 0

80.000 ns 0 8 0

80.000 ns 1 8 2

90.000 ns 0 9 2

90.000 ns 1 9 3

100.000 ns 0 A 3

100.000 ns 1 A 0

110.000 ns 0 B 0

110.000 ns 1 B 3

120.000 ns 0 C 3

130.000 ns 0 D 3

130.000 ns 1 D 4

140.000 ns 0 E 4

140.000 ns 1 E 1

150.000 ns 0 F 1

150.000 ns 1 F 6

160.000 ns 0 0 6

160.000 ns 1 0 0

170.000 ns 0 1 0

170.000 ns 1 1 3

1 2

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