+ $G_DPWR
+ $G_DGND
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Analog/Digital interface for node $N_0002
* Moving X_U7A.U1:IN2 from analog node $N_0002 to new digital node $N_0002$AtoD
X$$N_0002_AtoD1
+ $N_0002
+ $N_0002$AtoD
+ $G_DPWR
+ $G_DGND
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U10A.U1:IN2 from analog node $N_0002 to new digital node $N_0002$AtoD2
X$$N_0002_AtoD2
+ $N_0002
+ $N_0002$AtoD2
+ $G_DPWR
+ $G_DGND
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U9A.U1:IN2 from analog node $N_0002 to new digital node $N_0002$AtoD3
X$$N_0002_AtoD3
+ $N_0002
+ $N_0002$AtoD3
+ $G_DPWR
+ $G_DGND
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Analog/Digital interface for node $N_0013
* Moving X_U19A.U1:IN2 from analog node $N_0013 to new digital node $N_0013$AtoD
X$$N_0013_AtoD1
+ $N_0013
+ $N_0013$AtoD
+ $G_DPWR
+ $G_DGND
+ AtoD_STD
+ PARAMS: CAPACITANCE= 0
* Moving X_U21A.U1:OUT1 from analog node $N_0013 to new digital node $N_0013$DtoA
X$$N_0013_DtoA1
+ $N_0013$DtoA
+ $N_0013
+ $G_DPWR
+ $G_DGND
+ DtoA_STD
+ PARAMS: DRVH= 96.4 DRVL= 104 CAPACITANCE= 0
* Analog/Digital interface power supply subcircuits
X$DIGIFPWR 0 DIGIFPWR
**** 05/24/04 13:00:32 ******** PSpice 9.2.2 (May 2001) ******* ID# 777164219
* Z:\Sapr\lab9\my2\Schematic1.sch
**** Diode MODEL PARAMETERS
******************************************************************************
D74CLMP D74
IS 1.000000E-15 100.000000E-18
RS 2 25
CJO 2.000000E-12 2.000000E-12
**** 05/24/04 13:00:32 ******** PSpice 9.2.2 (May 2001) ******* ID# 777164219
* Z:\Sapr\lab9\my2\Schematic1.sch
**** BJT MODEL PARAMETERS
Q74
NPN
IS 100.000000E-18
BF 49
NF 1
ISE 100.000000E-18
BR .03
NR 1
ISC 400.000000E-18
RB 50
RC 20
CJE 1.000000E-12
VJE .9
MJE .5
CJC 500.000000E-15
VJC .8
CJS 3.000000E-12
VJS .7
MJS .33
TF 200.000000E-12
TR 10.000000E-09
CN 2.42
D .87
**** 05/24/04 13:00:32 ******** PSpice 9.2.2 (May 2001) ******* ID# 777164219
* Z:\Sapr\lab9\my2\Schematic1.sch
**** Digital Input MODEL PARAMETERS
******************************************************************************
DIN74
S0NAME 0
S0TSW 3.500000E-09
S0RLO 7.13
S0RHI 389
S1NAME 1
S1TSW 5.500000E-09
S1RLO 467
S1RHI 200
S2NAME X
S2TSW 3.500000E-09
S2RLO 42.9
S2RHI 116
S3NAME R
S3TSW 3.500000E-09
S3RLO 42.9
S3RHI 116
S4NAME F
S4TSW 3.500000E-09
S4RLO 42.9
S4RHI 116
S5NAME Z
S5TSW 3.500000E-09
S5RLO 200.000000E+03
S5RHI 200.000000E+03
**** 05/24/04 13:00:32 ******** PSpice 9.2.2 (May 2001) ******* ID# 777164219
* Z:\Sapr\lab9\my2\Schematic1.sch
**** Digital Output MODEL PARAMETERS
******************************************************************************
DO74
TIMESTEP 100.000000E-12
S0NAME X
S0VHI 2
S0VLO .8
S1NAME 0
S1VHI .8
S1VLO -1.5
S2NAME R
S2VHI 1.4
S2VLO .8
S3NAME R
S3VHI 2
S3VLO 1.3
S4NAME X
S4VHI 2
S4VLO .8
S5NAME 1
S5VHI 7
S5VLO 2
S6NAME F
S6VHI 2
S6VLO 1.3
S7NAME F
S7VHI 1.4
S7VLO .8
**** 05/24/04 13:00:32 ******** PSpice 9.2.2 (May 2001) ******* ID# 777164219
* Z:\Sapr\lab9\my2\Schematic1.sch
**** Digital Gate MODEL PARAMETERS
*****************************************************************************
D_00 D_02 D_08 D_04
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