Проектирование специализированного микроконтроллера (Приложение к курсовой работе по дисциплине «Технические средства микропроцессорных систем»), страница 4

    elsif ready = '1' then

      start <= '1';

-- test case 1; correct result

--      b(3 downto 0) <= "1010";

--      a(2 downto 0) <= "101";

--      n <= d - 200000000;

-- test case 2

    b(7 downto 0) <= "10101001";

    a(3 downto 0) <= "1000";

--  test case 3

--    b(2 downto 0) <= "101";

--    a <= d - 30000;

--  test case 3

--      b <= d - 3000000;

--      a <= d - 200000000;

      n <= x"888880000000" & d(1023 downto 48);

    end if;

    if start = '1' then

      start <= '0';

    end if;

  end if;

end process;

end architecture;

Исходный текст файла « test_rng.vhd»

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity test is

end test;

architecture test_lfsr of test is

component lfsr_512 is

port(clk : in std_logic;

     ce  : in std_logic;

     reset_l : in std_logic;

     seed  : in std_logic_vector(511 downto 0);

     output : out std_logic_vector(511 downto 0));

end component;

signal clk : std_logic := '0';

signal reset_l : std_logic := '0';

signal ce : std_logic:= '1';

signal output : std_logic_vector(511 downto 0);

constant seed : std_logic_vector(511 downto 0) := x"0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef";

begin

clk <= not clk after 5 ns;

reset_l <= '1' after 20 ns;

ce <= not ce after 150 ns;

my_flsr : lfsr_512 port map(clk, ce, reset_l, seed, output);

end architecture;

Исходный текст файла « test_prime.vhd »

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity test is

end test;

architecture test_prime of test is

component prime_test

  port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        rand_in: IN std_logic_VECTOR(511 downto 0);

        rd_ack : in std_logic;

        rd_en : out std_logic;

        prime_valid : out std_logic;

        prime_out: OUT std_logic_VECTOR(511 downto 0));

end component;

signal clk : std_logic := '0';

signal reset_l : std_logic := '0';

signal rand_in, prime_out: std_logic_vector(511 downto 0);

signal prime_valid : std_logic;

signal start, ready, rd_en, rd_ack : std_logic;

constant c: std_logic_vector(511 downto 0) := (others => '0');

begin

 

clk <= not clk after 5 ns;

reset_l <= '1' after 20 ns;

my_prime_test : prime_test port map (clk, reset_l, start, ready, rand_in, rd_ack, rd_en, prime_valid, prime_out);

process(clk)

variable flag:std_logic;

variable count:integer;

begin

  if clk'event and clk = '1' then

    if reset_l = '0' then

      start <= '0';

      rand_in <= (others => '0');

      rd_ack <= '0';

      rand_in <= x"c" & x"0000" & c(490 downto 2) & "100";

      count := 1;

    elsif ready = '1' and count < 5 then

      start <= '1';

    elsif rd_en = '1' then

      start <= '0';

      rd_ack <= '1';

      if count = 1 then

        rand_in <= x"c00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002f9";

      else

        rand_in <= c + count;

      end if;

      count := count + 1;

      flag := '1';

    elsif flag = '1' then

      rd_ack <= '0';

      flag := '0';

    else

      start <= '0';

    end if;

  end if;

end process;

end architecture;