Проектирование специализированного микроконтроллера (Приложение к курсовой работе по дисциплине «Технические средства микропроцессорных систем»), страница 3

-- test case 4; correct result

--      b(7 downto 0) <= "11110111";

--      a(3 downto 0) <= "1101";

--      n <= d - 200000000;

-- test case 1, 2, 3

--    b <= b + 300000000;

--    a <= a + d;

--  test case 2

--    n <= d - 200000000;

--  test case 3

      b <= d - 300000000;

      a <= d + a;

      n <= x"888880000000" & d(1023 downto 48);

    end if;

    if start = '1' then

      start <= '0';

    end if;

  end if;

end process;

end architecture;

Исходный текст файла «test_mul_1024.vhd »

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity test is

end test;

architecture test_mul_1024 of test is

component mult_1024

  port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        B: IN std_logic_VECTOR(1023 downto 0);

        M_valid : out std_logic;

        M: OUT std_logic_VECTOR(1023 downto 0));

end component;

signal clk : std_logic := '0';

signal reset_l : std_logic := '0';

signal a,b,m: std_logic_vector(1023 downto 0);

signal m_valid : std_logic;

signal start, ready : std_logic;

signal d: std_logic_vector(511 downto 0);

constant c: std_logic_vector(511 downto 0) := (others => '0');

begin

clk <= not clk after 5 ns;

reset_l <= '1' after 20 ns;

my_mod_mult : mult_1024 port map (clk, reset_l, start, ready, a, b, m_valid, m);

process(clk)

begin

  if clk'event and clk = '1' then

    if reset_l = '0' then

      b <= (others => '0');

      a <= (others => '0');

      d <= x"8" & x"0000" & c(491 downto 0);

    elsif ready = '1' then

      start <= '1';

-- test case 4; correct result

--      b(0) <= '1';

--      a(2 downto 0) <= "101";

-- test case 1, 2, 3

    b <= c(511 downto 0) & "11" & c(509 downto 3) & "101";

    a <= c(511 downto 0) & "1101" & c(507 downto 0);

--  test case 2

--    n <= d - 200000000;

--  test case 3

--    n <= x"888880000000" & d(511 downto 48);

    end if;

    if start = '1' then

      start <= '0';

    end if;

  end if;

end process;

end architecture;

Исходный текст файла « test_mod_exp_1024.vhd »

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity test is

end test;

architecture test_mod_exp of test is

component mod_exp_1024

  port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        B: IN std_logic_VECTOR(1023 downto 0);

        N: IN std_logic_VECTOR(1023 downto 0);

        E_valid : out std_logic;

        E: OUT std_logic_VECTOR(1023 downto 0));

end component;

signal clk : std_logic := '0';

signal reset_l : std_logic := '0';

signal a,b,e,n: std_logic_vector(1023 downto 0);

signal e_valid : std_logic;

signal start, ready : std_logic;

signal d: std_logic_vector(1023 downto 0);

constant c: std_logic_vector(1023 downto 0) := (others => '1');

begin

clk <= not clk after 5 ns;

reset_l <= '1' after 20 ns;

my_mod_exp : mod_exp_1024 port map (clk, reset_l, start, ready, a, b, n, e_valid, e);

process(clk)

begin

  if clk'event and clk = '1' then

    if reset_l = '0' then

      b <= (others => '0');

      a <= (others => '0');

      n <= (others => '0');

      d <= x"8" & x"0000" & c(1003 downto 0);