Проектирование и моделирование VHDL-описаний интегральных схем, страница 5

               port map(A(1)=>A,A(2)=>B,Y=>outs);

               Y<=outs after 5ns;

end;

architecture NMX2 of NMX2 is

signal valve1:std_logic;

signal valve2:std_logic;

signal NV:std_logic;

signal outs:std_logic;

begin

               NV<=not V;

               XX_NMX2_A2_1:XX

               generic map(2,op_and,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>NV,Y=>valve1);

               XX_NMX2_A2_2:XX

               generic map(2,op_and,pin_dir,pin_dir)

               port map(A(1)=>B,A(2)=>V,Y=>valve2);

               XX_NMX2_NO2:XX

               generic map(2,op_or,pin_dir,pin_inv)

               port map(A(1)=>valve1,A(2)=>valve2,Y=>outs);

               Y<=outs after 6ns;

end;

architecture NMX4 of NMX4 is

signal valve1:std_logic;

signal valve2:std_logic;

signal valve3:std_logic;

signal valve4:std_logic;

signal NV1:std_logic;

signal NV2:std_logic;

signal outs:std_logic;

begin

               NV1<=not V1;

               NV2<=not V2;

               XX_NMX4_A3_1:XX

               generic map(3,op_and,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>NV1,A(3)=>NV2,Y=>valve1);

               XX_NMX4_A3_2:XX

               generic map(3,op_and,pin_dir,pin_dir)

               port map(A(1)=>B,A(2)=>NV1,A(3)=>V2,Y=>valve2);

               XX_NMX4_A3_3:XX

               generic map(3,op_and,pin_dir,pin_dir)

               port map(A(1)=>C,A(2)=>V1,A(3)=>NV2,Y=>valve3);

               XX_NMX4_A3_4:XX

               generic map(3,op_and,pin_dir,pin_dir)

               port map(A(1)=>D,A(2)=>V1,A(3)=>V2,Y=>valve4);

               XX_NMX2_NO4:XX

               generic map(4,op_or,pin_dir,pin_inv)

               port map(A(1)=>valve1,A(2)=>valve2,A(3)=>valve3,A(4)=>valve4,Y=>outs);

               Y<=outs after 8ns;

end;

architecture NO2 of NO2 is

signal outs:std_logic;

begin

               XX_NO2:XX

               generic map(2,op_or,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>B,Y=>outs);

               Y<=outs after 3ns;

end;

architecture NO3 of NO3 is

signal outs:std_logic;

begin

               XX_NO3:XX

               generic map(3,op_or,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>B,A(3)=>C,Y=>outs);

               Y<=outs after 4ns;

end;

architecture NO3A2 of NO3A2 is

signal res1:std_logic;

signal outs:std_logic;

begin

               XX_NO3A2_A2:XX

               generic map(2,op_and,pin_dir,pin_dir)

               port map(A(1)=>C,A(2)=>D,Y=>res1);

               XX_NO3A2_NO3:XX

               generic map(3,op_or,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>B,A(3)=>res1,Y=>outs);

               Y<=outs after 5ns;

end;

architecture NO4 of NO4 is

signal outs:std_logic;

begin

               XX_NO4:XX

               generic map(4,op_or,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>B,A(3)=>C,A(4)=>D,Y=>outs);

               Y<=outs after 5ns;

end;

architecture NOA2 of NOA2 is

signal res1:std_logic;

signal outs:std_logic;

begin

               XX_NOA2_A2:XX

               generic map(2,op_and,pin_dir,pin_dir)

               port map(A(1)=>B,A(2)=>C,Y=>res1);

               XX_NOA2_NO2:XX

               generic map(2,op_or,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>res1,Y=>outs);

               Y<=outs after 3ns;

end;

architecture NOA22 of NOA22 is

signal res1:std_logic;

signal res2:std_logic;

signal outs:std_logic;

begin

               XX_NOA22_A2_1:XX

               generic map(2,op_and,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>B,Y=>res1);

               XX_NOA22_A2_2:XX

               generic map(2,op_and,pin_dir,pin_dir)

               port map(A(1)=>C,A(2)=>D,Y=>res2);

               XX_NOA22_NO2:XX

               generic map(2,op_or,pin_dir,pin_inv)

               port map(A(1)=>res1,A(2)=>res2,Y=>outs);

               Y<=outs after 4ns;

end;

architecture NOA3 of NOA3 is

signal res1:std_logic;

signal outs:std_logic;

begin

               XX_NOA3_A3:XX

               generic map(3,op_and,pin_dir,pin_dir)

               port map(A(1)=>B,A(2)=>C,A(3)=>D,Y=>res1);

               XX_NOA3_NO2:XX

               generic map(2,op_or,pin_dir,pin_inv)