DMA для dsPIC. Контроллер Прямого доступа к памяти (DMA). DMA контроллер. Регистр Смещения Адреса Начала A DPSRAM Канала DMA x, страница 3

1000111 = ECAN2       – TX данные отправлены

Примечание 1: бит FORCE не может быть очищен пользователем. бит FORCE очищается аппаратно когда передача DMA выполнена.

Регистр 3: DMAxSTA: Регистр Смещения Адреса Начала A DPSRAM Канала DMA x

бит 15-0 STA<15:0>: первое смещение начала адреса DPSRAM (источник или приёмник)

Регистр 4: DMAxSTB: Регистр Смещения Адреса Начала B DPSRAM Канала DMA x

бит 15-0 STB<15:0>: второе смещение адреса начала DPSRAM (источник или приёмник)

Регистр 5: DMAXPAD: Регистр адреса Периферии Канала DMA x

бит 15-0 PAD<15:0>: регистр адреса перефирии

Регистр 6: DMAXCNT: Регистр Счетчика Передачи Канала DMA x

бит 15-10 Зарезервировано

бит 9-0 CNT<9:0>: биты регистра счётчика DMA

Регистр 7: DSADR: Адрес последнего DMA DPSRAM к которому обращались

bit 15-0 DSADR<15:0>: биты Адреса последнего DMA DPSRAM к которому обращались

Регистр 8: DMACS0: Регистр состояния 0 контроллера DMA

bit 15 PWCOL7: Channel 7 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 14 PWCOL6: Channel 6 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 13 PWCOL5: Channel 5 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 12 PWCOL4: Channel 4 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 11 PWCOL3: Channel 3 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 10 PWCOL2: Channel 2 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 9 PWCOL1: Channel 1 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 8 PWCOL0: Channel 0 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 7 XWCOL7: Channel 7 DPSRAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 6 XWCOL6: Channel 6 DPSRAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 5 XWCOL5: Channel 5 DPSRAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 4 XWCOL4: Channel 4 DPSRAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 3 XWCOL3: Channel 3 DPSRAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 2 XWCOL2: Channel 2 DPSRAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 1 XWCOL1: Channel 1 DPSRAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 0 XWCOL0: Channel 0 DPSRAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

Register 22-8: DMACS0: DMA Controller Status Register 0 (Continued)

Register 22-9: DMACS1: DMA Controller Status Register 1

 bit 15-12 Unimplemented: Read as ‘0’

bit 11-8 LSTCH<3:0>: Last DMAC Channel Active bits

1111 = No DMA transfer has occurred since system reset

1110-1000 = Reserved

0111 = Last data transfer was by Channel 7

0110 = Last data transfer was by Channel 6

0101 = Last data transfer was by Channel 5

0100 = Last data transfer was by Channel 4

0011 = Last data transfer was by Channel 3

0010 = Last data transfer was by Channel 2

0001 = Last data transfer was by Channel 1

0000 = Last data transfer was by Channel 0

Set to ‘1111’ at Reset. This field is accessible at any time but is primarily intended as a debugging aid.

bit 7 PPST7: Channel 7 ‘Ping-Pong’ Mode Status Flag

1 = DMA7STB register selected

0 = DMA7STA register selected

bit 6 PPST6: Channel 6 ‘Ping-Pong’ Mode Status Flag

1 = DMA6STB register selected

0 = DMA6STA register selected

bit 5 PPST5: Channel 5 ‘Ping-Pong’ Mode Status Flag