Описание элементов. Логический элемент «8И-НЕ» К155ЛА2 . Программируемый параллельный интерфейс КР580ВВ55, страница 4

m1<= transport not ( k1 or l1 ) after 20ns;

m2<= transport not ( k2 or l2 ) after 20ns;

m3<= transport not ( k3 or l3 ) after 20ns;

m4<= transport not ( k4 or l4 ) after 20ns;

end k559ip2p;

k589ap26

library IEEE;

use IEEE.std_logic_1164.all;

entity k589ap26 is

port (

cs: in STD_LOGIC;

bs: in STD_LOGIC;

di: in STD_LOGIC_VECTOR (3 downto 0);

db: inout STD_LOGIC_VECTOR (3 downto 0);

do: out STD_LOGIC_VECTOR (3 downto 0)

);

end k589ap26;

architecture k589ap26 of k589ap26 is

begin

process (cs, bs, db, di)

begin

If (cs='0')and(bs='0') then

db<= transport di after 50 ns;

end if;

If (cs='0')and(bs='1') then

do<= transport db after 50 ns;

end if;

end process; 

end k589ap26;

kr580vv55

library IEEE;

use IEEE.std_logic_1164.all;

entity kr580vv55 is

port (

pa: inout STD_LOGIC_VECTOR (7 downto 0);

pb: inout STD_LOGIC_VECTOR (7 downto 0);

pc: inout STD_LOGIC_VECTOR (7 downto 0);

pd: inout STD_LOGIC_VECTOR (7 downto 0);

cs: in STD_LOGIC;

rd: in STD_LOGIC;

wr: in STD_LOGIC;

a1: in STD_LOGIC;

a0: in STD_LOGIC

);

end kr580vv55;

architecture kr580vv55 of kr580vv55 is

begin

process (cs, rd, wr, a1, a0, pa, pb, pc)

begin

If (cs='0') and (rd='1') and (wr='0') and (a1='0')and(a0='0') then

pa<= transport pd after 20ns;

end If;

If (cs='0')and(rd='1')and(wr='0')and(a1='0')and(a0='1') then

pb<= transport pd after 20ns;

end If;

If (cs='0')and(rd='1')and(wr='0')and(a1='1')and(a0='0') then

pc<= transport pd after 20ns;

end If;

If (cs='0')and(rd='0')and(wr='1')and(a1='0')and(a0='0') then

pd<= transport pa after 20ns;

end If;

If (cs='0')and(rd='0')and(wr='1')and(a1='0')and(a0='1') then

pd<= transport pb after 20ns;

end If;

If (cs='0')and(rd='0')and(wr='1')and(a1='1')and(a0='0') then

pd<= transport pc after 20ns;

end If;

end process;   

end kr580vv55;

Top

library IEEE;

use  IEEE.std_logic_1164.all;

use  IEEE.std_logic_unsigned.all;

entity Top is

port (

vh0,vh1,vh2,vh3,vh4,vh5,vh6,vh7,vh8,vh9,vh10,vh11,vh12,vh13,vh14,vh15,

vh16,vh17,vh18,vh19: inout STD_LOGIC;

vd0,vd1,vd2,vd3,vd4,vd5,vd6,vd7,vd8,vd9,vd10,vd11,vd12,vd13,vd14,vd15,

vd16,vd17,vd18,vd19,vd20,vd21,vd22,vd23: inout STD_LOGIC

);

end Top;

architecture Structure of Top is

component d56 is

port (

q1: in STD_LOGIC;

q2: in STD_LOGIC;

q3: out STD_LOGIC

);

end component;

component k155la3 is

port (

f1: in STD_LOGIC;

f2: in STD_LOGIC;

f3: in STD_LOGIC;

f4: in STD_LOGIC;

v1: in STD_LOGIC;

v2: in STD_LOGIC;

v3: in STD_LOGIC;

v4: in STD_LOGIC;

z1: out STD_LOGIC;

z2: out STD_LOGIC;

z3: out STD_LOGIC;

z4: out STD_LOGIC

);

end component;

component k155la8  is

port (

t1: in STD_LOGIC;

t2: in STD_LOGIC;

t3: in STD_LOGIC;

t4: in STD_LOGIC;

e1: in STD_LOGIC;

e2: in STD_LOGIC;

e3: in STD_LOGIC;

e4: in STD_LOGIC;

w1: out STD_LOGIC;

w2: out STD_LOGIC;

w3: out STD_LOGIC;

w4: out STD_LOGIC

);

end component;

component k155la2 is

port (

A: in STD_LOGIC;

B: in STD_LOGIC;

C: in STD_LOGIC;

D: in STD_LOGIC;

E: in STD_LOGIC;

F: in STD_LOGIC;

H: in STD_LOGIC;

G: in STD_LOGIC;

Y: out STD_LOGIC

);

end component;

component k559ip2p is

port (

k1: in STD_LOGIC;

k2: in STD_LOGIC;

k3: in STD_LOGIC;

k4: in STD_LOGIC;

l1: in STD_LOGIC;

l2: in STD_LOGIC;

l3: in STD_LOGIC;

l4: in STD_LOGIC;

m1: out STD_LOGIC;

m2: out STD_LOGIC;

m3: out STD_LOGIC;

m4: out STD_LOGIC

);

end component;

component k589ap26 is

port (

cs: in STD_LOGIC;

bs: in STD_LOGIC;

di: in STD_LOGIC_VECTOR (3 downto 0);

db: inout STD_LOGIC_VECTOR (3 downto 0);