Информатика и выч. техника \ Теория проектирования ЭВМ

Проектирование мультипроцессорного арбитра шины, страница 2

CLOCKF CLK

SETF RB0 CLK

CLOCKF CLK

SETF /RESET CLK

CLOCKF CLK

SETF /RA1 /RA2 /RA3 /RA4 /RA0 /RB0 /RB1 /RB2 /SACK CLK

CLOCKF CLK

SETF RA1 RESET SACK CLK

CLOCKF CLK

SETF RA2 /RESET /SACK CLK

CLOCKF CLK

INTEL Logic Optimizing Compiler Utilization Report arbiter.rpt

***** Design implemented successfully

PLD22V10

- - - - CLK -| 1 24|- Vcc

SACK -| 2 23|- Gnd

RB2 -| 3 22|- Gnd

RB1 -| 4 21|- BG0

RB0 -| 5 20|- BG1

RA4 -| 6 19|- BG2

RA3 -| 7 18|- BG3

RA2 -| 8 17|- BG4

RA1 -| 9 16|- BG5

RA0 -|10 15|- BG6

RESET -|11 14|- BG7

GND -|12 13|- Gnd

- - - - CMOS Device: ground unused inputs and I/Os Gnd = unused input or I/O pin.

RESERVED = Leave pins unconnected on board. N.C. = unconnected pins

arbiter.rpt

**OUTPUTS**

Name Pin Resource MCell PTerms | Sync Clock

BG0 21 RORF 7 2/12 | CLK

BG1 20 RORF 6 2/14 | CLK

BG2 19 RORF 5 2/16 | CLK

BG3 18 RORF 4 2/16 | CLK

BG4 17 RORF 3 2/14 | CLK

BG5 16 RORF 2 2/12 | CLK

BG6 15 RORF 1 2/10 | CLK

BG7 14 RORF 0 2/ 8 | CLK

arbiter.rpt

**INPUTS**

Name Pin Resource MCell PTerms | Sync Clock

RESET 11 INP - - | -

RA0 10 INP - - | -

RA1 9 INP - - | -

RA2 8 INP - - | -

RA3 7 INP - - | -

RA4 6 INP - - | -

RB0 5 INP - - | -

RB1 4 INP - - | -

RB2 3 INP - - | -

SACK 2 INP - - | -

CLK 1 INP - - | -

**UNUSED RESOURCES**

Name Pin Resource MCell PTerms

- 13 INPUT - -

- 22 MCELL 8 10

- 23 MCELL 9 8

**PART UTILIZATION**

8/10 MacroCells (80%), 15% of used Pterms Filled

11/12 Input Pins (91%)

PTerms Used 13%

**RESOURCE MNEMONICS**

INP = Pin Input to Logic Array

RORF = D-Register pin Output, Register Feedback

Macrocell Interconnection Cross Reference arbiter.rpt

FEEDBACKS: M M M M M M M M

0 0 0 0 0 0 0 0

0 1 2 3 4 5 6 7

BG7 ...... RORF @M0 -> * * * * * * * * @14

BG6 ...... RORF @M1 -> * * * * * * * * @15

BG5 ...... RORF @M2 -> * * * * * * * * @16

BG4 ...... RORF @M3 -> * * * * * * * * @17

BG3 ...... RORF @M4 -> * * * * * * * * @18

BG2 ...... RORF @M5 -> * * * * * * * * @19

BG1 ...... RORF @M6 -> * * * * * * * * @20

BG0 ...... RORF @M7 -> * * * * * * * * @21

INPUTS:

CLK ...... INP @1 -> * * * * * * * *

SACK ..... INP @2 -> * * * * * * * *

RB2 ...... INP @3 -> * . . . . . . .

RB1 ...... INP @4 -> * * . . . . . .

RB0 ...... INP @5 -> * * * . . . . .

RA4 ...... INP @6 -> * * * * . . . .

RA3 ...... INP @7 -> * * * * * . . .

RA2 ...... INP @8 -> * * * * * * . .

RA1 ...... INP @9 -> * * * * * * * .

RA0 ...... INP @10 -> * * * * * * * *

RESET .... INP @11 -> * * * * * * * *

B B B B B B B B

G G G G G G G G

7 6 5 4 3 2 1 0

. = not connected x = no connection possible

* = signal feeds cell ? = error, unable to fit

Title Local Bus Controller Example

Pattern pds

Revision 1

Author Your Name

Company Your Company

Date Date

CHIP BUS_CON1 pld22v10

PIN CLK

PIN RESET

PIN RA0

PIN RA1

PIN RA2

PIN RA3

PIN RA4

PIN RB0

PIN RB1

PIN RB2

PIN SACK

PIN BG0

PIN BG1

PIN BG2

PIN BG3

PIN BG4

PIN BG5

PIN BG6

PIN BG7

;**********

STATE

MOORE_MACHINE

;состояние по умолчанию

DEFAULT_BRANCH S00

;описание состояний

S00 = /BG0

S1 = BG0

;описание переходов

S00 := UP1 ->S1

+ SS1 ->S00

S1 := DOWN1 ->S00

+ SSS1 ->S1

CONDITIONS

SSS1 = SACK

SS1=/SACK*/RA0*/RA1*/RA2*/RA3*/RA4*/RB0*/RA1*/RB2

UP1 = RA0*SACK*/bg1*/bg2*/bg3*/bg4*/bg3*/bg4*/bg5*/bg6*/bg7

DOWN1 = /SACK*RESET

STATE

MOORE_MACHINE

;состояние по умолчанию

DEFAULT_BRANCH S01

;описание состояний

1 2 3

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