Изучение среды моделирования Aldec Active HDL, страница 4

Y2<= (x2 and not x4) or (not x4 and x3)

Y3		x2x1
x4x3		00	01	11	10
	00	0	0	1	X
	01	x	x	x	1
	11	1	1	0	0
	10	0	0	0	0

Y3<=(not x2 and x3) or (x2 and not x4)

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library IEEE;

use IEEE.std_logic_1164.all;

entity nya is

      port (

            x1: in STD_LOGIC;

            x2: in STD_LOGIC;

            x3: in STD_LOGIC;

            x4: in STD_LOGIC;

            y1: out STD_LOGIC;

            y2: out STD_LOGIC;

            y3: out STD_LOGIC

      );

end nya;

architecture nya of nya is

begin

      y1<=(not x2 and not x4) or (not x1 and not x2 and x3) or (x1 and not x3 and not x4);

      y2<=(x2 and not x4) or (not x4 and x3);

      y3<=(not x2 and x3) or (x2 and not x4);