Проектирование специализированного микроконтроллера

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port   (up_in_pht, down_in_pht       : in std_logic_vector(31 downto 0);

        up_out_pht, down_out_pht     : out std_logic_vector(31 downto 0));

end pht;

-- architecture description

architecture pht_arch of pht is

       -- we declare internal signals

       signal intermediate_carry1, intermediate_carry2,

                      to_upper_out                  : std_logic_vector(31 downto 0);

       signal zero                                 : std_logic;

       component adder

       port   (in1_adder, in2_adder,        in_carry_adder : in std_logic;

                out_adder, out_carry_adder   : out std_logic);

       end component;

begin

       -- initializing zero signal

       zero <= '0';

       -- instantiating the upper adder of 32 bits

       up_adder: for i in 0 to 31 generate

               adder_one: if (i=0) generate

                      the_adder: adder

                      port map       (

                                            in1_adder => up_in_pht(0),

                                            in2_adder => down_in_pht(0),

                                            in_carry_adder => zero,

                                            out_adder => to_upper_out(0),

                                            out_carry_adder => intermediate_carry1(0)

                                            );

               end generate adder_one;

               rest_adders: if (i>0) generate

                      next_adder: adder

                      port map       (

                                            in1_adder => up_in_pht(i),

                                            in2_adder => down_in_pht(i),

                                            in_carry_adder => intermediate_carry1(i-1),

                                            out_adder => to_upper_out(i),

                                            out_carry_adder => intermediate_carry1(i)

                                            );

               end generate rest_adders;

       end generate up_adder;

       intermediate_carry1(31) <= '0';

       -- receiving the upper pht output

       up_out_pht <= to_upper_out;

       -- instantiating the lower adder of 32 bits

       down_adder: for i in 0 to 31 generate

               adder_one_1: if (i=0) generate

                      the_adder_1: adder

                      port map       (

                                            in1_adder => down_in_pht(0),

                                            in2_adder => to_upper_out(0),

                                            in_carry_adder => zero,

                                            out_adder => down_out_pht(0),

                                            out_carry_adder => intermediate_carry2(0)

                                            );

               end generate adder_one_1;

               rest_adders_1: if (i>0) generate

                      next_adder_1: adder

                      port map       (

                                            in1_adder => down_in_pht(i),

                                            in2_adder => to_upper_out(i),

                                            in_carry_adder => intermediate_carry2(i-1),

                                            out_adder => down_out_pht(i),

                                            out_carry_adder => intermediate_carry2(i)

                                            );

               end generate rest_adders_1;

       end generate down_adder;

       intermediate_carry2(31) <= '0';

end pht_arch;

-- new component - multiplier by 01 --                                          

library ieee;

use ieee.std_logic_1164.all;

entity mul01 is

port   (in_mul01      : in std_logic_vector(7 downto 0);

       out_mul01      : out std_logic_vector(7 downto 0));

end mul01;

architecture mul01_arch of mul01 is

begin

       out_mul01 <= in_mul01;

end mul01_arch;

-- new component - multiplier by a4 --                                          

library ieee;

use ieee.std_logic_1164.all;

entity mula4 is

port   (in_mula4      : in std_logic_vector(7 downto 0);                 

       out_mula4      : out std_logic_vector(7 downto 0));

end mula4;

architecture mula4_arch of mula4 is

begin

       out_mula4(0) <= in_mula4(7) xor in_mula4(1);

       out_mula4(1) <= in_mula4(2);

       out_mula4(2) <= in_mula4(7) xor in_mula4(3) xor in_mula4(1) xor in_mula4(0);

       out_mula4(3) <= in_mula4(7) xor in_mula4(4) xor in_mula4(2);

       out_mula4(4) <= in_mula4(5) xor in_mula4(3);

       out_mula4(5) <= in_mula4(6) xor in_mula4(4) xor in_mula4(0);

       out_mula4(6) <= in_mula4(5);

       out_mula4(7) <= in_mula4(6) xor in_mula4(0);

end mula4_arch;

-- new component - multiplier by 55 --                                          

library ieee;

use ieee.std_logic_1164.all;

entity mul55 is

port   (in_mul55      : in std_logic_vector(7 downto 0);

       out_mul55      : out std_logic_vector(7 downto 0));

end mul55;

architecture mul55_arch of mul55 is

begin

       out_mul55(0) <= in_mul55(7) xor in_mul55(6) xor in_mul55(2) xor in_mul55(0);

       out_mul55(1) <= in_mul55(7) xor in_mul55(3) xor in_mul55(1);

       out_mul55(2) <= in_mul55(7) xor in_mul55(6) xor in_mul55(4) xor in_mul55(0);

       out_mul55(3) <= in_mul55(6) xor in_mul55(5) xor in_mul55(2) xor in_mul55(1);

       out_mul55(4) <= in_mul55(7) xor in_mul55(6) xor in_mul55(3) xor in_mul55(2) xor in_mul55(0);

       out_mul55(5) <= in_mul55(7) xor in_mul55(4) xor in_mul55(3) xor in_mul55(1);

       out_mul55(6) <= in_mul55(7) xor in_mul55(6) xor in_mul55(5) xor in_mul55(4) xor in_mul55(0);

       out_mul55(7) <= in_mul55(7) xor in_mul55(6) xor in_mul55(5) xor in_mul55(1);

end mul55_arch;

-- new component - multiplier by 87  --                                         

library ieee;

use ieee.std_logic_1164.all;

entity mul87 is

port   (in_mul87      : in std_logic_vector(7 downto 0);

       out_mul87      : out std_logic_vector(7 downto 0));

end mul87;

architecture mul87_arch of mul87 is

begin

       out_mul87(0) <= in_mul87(7) xor in_mul87(5) xor in_mul87(3) xor in_mul87(1) xor in_mul87(0);

       out_mul87(1) <= in_mul87(6) xor in_mul87(4) xor in_mul87(2) xor in_mul87(1) xor in_mul87(0);

       out_mul87(2) <= in_mul87(2) xor in_mul87(0);

       out_mul87(3) <= in_mul87(7) xor in_mul87(5);

       out_mul87(4) <= in_mul87(6);

       out_mul87(5) <= in_mul87(7);

       out_mul87(6) <= in_mul87(7) xor in_mul87(5) xor in_mul87(3) xor in_mul87(1);

       out_mul87(7) <= in_mul87(6) xor in_mul87(4) xor in_mul87(2) xor in_mul87(0);

end mul87_arch;

-- new component - multiplier by 5a --                                   

library ieee;

use ieee.std_logic_1164.all;

entity mul5a is

port   (in_mul5a      : in std_logic_vector(7 downto 0);

       out_mul5a      : out std_logic_vector(7 downto 0));

end mul5a;

architecture mul5a_arch of mul5a is

begin

       out_mul5a(0) <= in_mul5a(7) xor in_mul5a(5) xor in_mul5a(2);

       out_mul5a(1) <= in_mul5a(6) xor in_mul5a(3) xor in_mul5a(0);

       out_mul5a(2) <= in_mul5a(5) xor in_mul5a(4) xor in_mul5a(2) xor in_mul5a(1);

       out_mul5a(3) <= in_mul5a(7) xor in_mul5a(6) xor in_mul5a(3) xor in_mul5a(0);

       out_mul5a(4) <= in_mul5a(7) xor in_mul5a(4) xor in_mul5a(1) xor in_mul5a(0);

       out_mul5a(5) <= in_mul5a(5) xor in_mul5a(2) xor in_mul5a(1);

       out_mul5a(6) <= in_mul5a(7) xor in_mul5a(6) xor in_mul5a(5) xor in_mul5a(3) xor in_mul5a(0);

       out_mul5a(7) <= in_mul5a(7) xor in_mul5a(6) xor in_mul5a(4) xor in_mul5a(1);

end mul5a_arch;

-- new component - multiplier by 58 --                                   

library ieee;

use ieee.std_logic_1164.all;

entity mul58 is

port   (in_mul58      : in std_logic_vector(7 downto 0);

       out_mul58      : out std_logic_vector(7 downto 0));

end mul58;

architecture mul58_arch of mul58 is

begin

       out_mul58(0) <= in_mul58(5) xor in_mul58(2);

       out_mul58(1) <= in_mul58(6) xor in_mul58(3);

       out_mul58(2) <= in_mul58(7) xor in_mul58(5) xor in_mul58(4) xor in_mul58(2);

       out_mul58(3) <= in_mul58(6) xor in_mul58(3) xor in_mul58(2) xor in_mul58(0);

       out_mul58(4) <= in_mul58(7) xor in_mul58(4) xor in_mul58(3) xor in_mul58(1) xor in_mul58(0);

       out_mul58(5) <= in_mul58(5) xor in_mul58(4) xor in_mul58(2) xor in_mul58(1);

       out_mul58(6) <= in_mul58(6) xor in_mul58(3) xor in_mul58(0);

       out_mul58(7) <= in_mul58(7) xor in_mul58(4) xor in_mul58(1);

end mul58_arch;

-- new component - multiplier by db --                                          

library ieee;

use ieee.std_logic_1164.all;

entity muldb is

port   (in_muldb      : in std_logic_vector(7 downto 0);

       out_muldb      : out std_logic_vector(7 downto 0));

end muldb;

architecture muldb_arch of muldb is

begin

       out_muldb(0) <= in_muldb(7) xor in_muldb(6) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);

       out_muldb(1) <= in_muldb(7) xor in_muldb(4) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);

       out_muldb(2) <= in_muldb(7) xor in_muldb(6) xor in_muldb(5) xor in_muldb(4);

       out_muldb(3) <= in_muldb(5) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);

       out_muldb(4) <= in_muldb(6) xor in_muldb(4) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0);

       out_muldb(5) <= in_muldb(7) xor in_muldb(5) xor in_muldb(4) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1);

       out_muldb(6) <= in_muldb(7) xor in_muldb(5) xor in_muldb(4) xor in_muldb

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