case (AND2_1)is
when '1' => \Y_-1\<=AND2_1 after 22 ns; --Tplh
when '0' => \Y_-1\<=AND2_1 after 17 ns; --Tphl
end case;
end if;
end process;
process(\A_-2\,\B_-2\,\Y_-2\,AND2_2) begin
AND2_2<=(\A_-2\and\B_-2\);
if (AND2_2'EVENT) then -- проверка на переключение сигналов
case (AND2_2)is
when '1' => \Y_-2\<=AND2_2 after 22 ns; --Tplh
when '0' => \Y_-2\<=AND2_2 after 17 ns; --Tphl
end case;
end if;
end process;
process(\A_-3\,\B_-3\,\Y_-3\,AND2_3) begin
AND2_3<=(\A_-3\and\B_-3\);
if (AND2_3'EVENT) then -- проверка на переключение сигналов
case (AND2_3)is
when '1' => \Y_-3\<=AND2_3 after 22 ns; --Tplh
when '0' => \Y_-3\<=AND2_3 after 17 ns; --Tphl
end case;
end if;
end process;
process(\A_-4\,\B_-4\,\Y_-4\,AND2_4) begin
AND2_4<=(\A_-4\and\B_-4\);
if (AND2_4'EVENT) then -- проверка на переключение сигналов
case (AND2_4)is
when '1' => \Y_-4\<=AND2_4 after 22 ns; --Tplh
when '0' => \Y_-4\<=AND2_4 after 17 ns; --Tphl
end case;
end if;
end process;
END model;
***********************************Элемент 3И-НЕ*****************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY K555LA4 IS PORT(
\A3_-1\ : IN std_logic;
\A3_-2\ : IN std_logic;
\A3_-3\ : IN std_logic;
\B3_-1\ : IN std_logic;
\B3_-2\ : IN std_logic;
\B3_-3\ : IN std_logic;
\C3_-1\ : IN std_logic;
\C3_-2\ : IN std_logic;
\C3_-3\ : IN std_logic;
\Y3_-1\ : OUT std_logic;
\Y3_-2\ : OUT std_logic;
\Y3_-3\ : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END K555LA4;
ARCHITECTURE model OF K555LA4 IS
BEGIN
\Y3_-1\ <= NOT ( \A3_-1\ AND \B3_-1\ AND \C3_-1\ ) AFTER 1 ns;
\Y3_-2\ <= NOT ( \A3_-2\ AND \B3_-2\ AND \C3_-2\ ) AFTER 1 ns;
\Y3_-3\ <= NOT ( \A3_-3\ AND \B3_-3\ AND \C3_-3\ ) AFTER 1 ns;
END model;
***********************************Элемент 3И********************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY K555LI3 IS PORT(
\A6_-1\ : IN std_logic;
\A6_-2\ : IN std_logic;
\A6_-3\ : IN std_logic;
\B6_-1\ : IN std_logic;
\B6_-2\ : IN std_logic;
\B6_-3\ : IN std_logic;
\C6_-1\ : IN std_logic;
\C6_-2\ : IN std_logic;
\C6_-3\ : IN std_logic;
\Y6_-1\ : OUT std_logic;
\Y6_-2\ : OUT std_logic;
\Y6_-3\ : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END K555LI3;
ARCHITECTURE model OF K555LI3 IS
SIGNAL AND3_1 : std_logic;
SIGNAL AND3_2 : std_logic;
SIGNAL AND3_3 : std_logic;
begin
process(\A6_-1\,\B6_-1\,\C6_-1\,\Y6_-1\,AND3_1) begin
AND3_1<=(\A6_-1\and\B6_-1\and\C6_-1\);
if (AND3_1'EVENT) then -- проверка на переключение сигналов
case (AND3_1)is
when '1' => \Y6_-1\<=AND3_1 after 12 ns; --Tplh
when '0' => \Y6_-1\<=AND3_1 after 10 ns; --Tphl
end case;
end if;
end process;
process(\A6_-2\,\B6_-2\,\C6_-2\,\Y6_-2\,AND3_2) begin
AND3_2<=(\A6_-2\and\B6_-2\and\C6_-2\);
if (AND3_2'EVENT) then -- проверка на переключение сигналов
case (AND3_2)is
when '1' => \Y6_-2\<=AND3_2 after 12 ns; --Tplh
when '0' => \Y6_-2\<=AND3_2 after 10 ns; --Tphl
end case;
end if;
end process;
process(\A6_-3\,\B6_-3\,\C6_-3\,\Y6_-3\,AND3_3) begin
AND3_3<=(\A6_-3\and\B6_-3\and\C6_-3\);
if (AND3_3'EVENT) then -- проверка на переключение сигналов
case (AND3_3)is
when '1' => \Y6_-3\<=AND3_3 after 12 ns; --Tplh
when '0' => \Y6_-3\<=AND3_3 after 10 ns; --Tphl
end case;
end if;
end process;
END model;
***********************************Элемент 4И-НЕ*****************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY K555LA1 IS PORT(
\A4_-1\ : IN std_logic;
\A4_-2\ : IN std_logic;
\B4_-1\ : IN std_logic;
\B4_-2\ : IN std_logic;
\C4_-1\ : IN std_logic;
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