Создание структурных и поведенческих моделей исследуемого цифрового узла (элемент К555ИМ3 (полный двоичный четырехразрядный сумматор)) в пакетах OrCAD 9.1, Active-HDL 8.1, страница 9

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* K555LA3  Quadruple 2-input Positive-Nand Gates

*

.subckt K555LA3  A B Y

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

U1 nand(2) DPWR DGND

+          A B   Y

+          D_LA3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

.model D_LA3 ugate (

+          tplhty=9ns      tplhmx=0ns

+          tphlty=10ns    tphlmx=0ns

+          )

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* K555LE1  Triple 2-input Positive-Nor Gates

*

.subckt K555LE1  A B Y

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

U1 nor(2) DPWR DGND

+          A B   Y

+          D_LE1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

*

.model D_LE1 ugate (

+          tplhty=10ns    tplhmx=0ns

+          tphlty=10ns    tphlmx=0ns

+          )

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* K555LE4  Triple 3-input Positive-Nor Gates

*

.subckt K555LE4  A B C Y

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

U1 nor(3) DPWR DGND

+          A B C   Y

+          D_LE4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

.model D_LE4 ugate (

+          tplhty=10ns    tplhmx=0ns

+          tphlty=10ns    tphlmx=0ns

+          )

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* K555LI1  Quadruple 2-input Positive-And Gates

.subckt K555LI1  A B Y

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

U1 and(2) DPWR DGND

+          A B   Y

+          D_LI1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

.model D_LI1 ugate (

+          tplhty=8ns      tplhmx=0ns

+          tphlty=10ns    tphlmx=0ns

+          )

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* K555LI1A  Quadruple 2-input Positive-And Gates

.subckt K555LI1A  A B Y

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

U1 and(2) DPWR DGND

+          A B   Y

+          D_LI1A IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

.model D_LI1A ugate (

+          tplhty=0ns      tplhmx=17ns

+          tphlty=0ns      tphlmx=17ns

+          )

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* K555LI3  Triple 3-input Positive-And Gates

.subckt K555LI3  A B C Y

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

U1 and(3) DPWR DGND

+          A B C   Y

+          D_LI3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

.model D_LI3 ugate (

+          tplhty=8ns      tplhmx=0ns

+          tphlty=10ns    tphlmx=0ns

+          )

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* K555LN1  Hex Inverters

.subckt K555LN1  A Y

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

U1 inv DPWR DGND

+          A   Y

+          D_LN1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

.model D_LN1 ugate (

+          tplhty=9ns      tplhmx=0ns

+          tphlty=10ns    tphlmx=0ns

+          )

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* K555LP5  Quadruple 2-input Exclusive-Or Gates

.subckt K555LP5  A B Y

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

UIBUF bufa(2) DPWR DGND

+          A B   A_BUF B_BUF