Создание структурных и поведенческих моделей исследуемого цифрового узла (элемент К555IM6 (двоичный 4-разрядный сумматор)) в пакетах DesignLab 8, OrCad 9.1, страница 9

    \OUT1_-2\ <= NOT ( \IN1_-2\ OR \IN2_-2\ );

    \OUT1_-3\ <= NOT ( \IN1_-3\ OR \IN2_-3\ );

    \OUT1_-4\ <= NOT ( \IN1_-4\ OR \IN2_-4\ );

END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \K555LN1\ IS

PORT(

            \IN1_-1\ : IN std_logic;

            \OUT1_-1\ : OUT std_logic;

            VCC : IN std_logic;

            GND : IN std_logic;

            \IN1_-2\ : IN std_logic;

            \OUT1_-2\ : OUT std_logic;

            \IN1_-3\ : IN std_logic;

            \OUT1_-3\ : OUT std_logic;

            \IN1_-4\ : IN std_logic;

            \OUT1_-4\ : OUT std_logic;

            \IN1_-5\ : IN std_logic;

            \OUT1_-5\ : OUT std_logic;

            \IN1_-6\ : IN std_logic;

            \OUT1_-6\ : OUT std_logic

);END \K555LN1\;

ARCHITECTURE model OF \K555LN1\ IS

    BEGIN                 

    \OUT1_-1\<= NOT( \IN1_-1\);   

    \OUT1_-2\<= NOT( \IN1_-2\);  

    \OUT1_-3\<= NOT( \IN1_-3\);  

    \OUT1_-4\<= NOT( \IN1_-4\);  

    \OUT1_-5\<= NOT( \IN1_-5\);  

    \OUT1_-6\<= NOT( \IN1_-6\);                                                   

 END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \K555LI6\ IS

PORT(

            \IN1_-1\ : IN std_logic;

            \IN2_-1\ : IN std_logic;

            \IN3_-1\ : IN std_logic;

            \IN4_-1\ : IN std_logic;

            \OUT1_-1\ : OUT std_logic;

            VCC : IN std_logic;

            GND : IN std_logic;

            \IN1_-2\ : IN std_logic;

            \IN2_-2\ : IN std_logic;

            \IN3_-2\ : IN std_logic;

            \IN4_-2\ : IN std_logic;

            \OUT1_-2\ : OUT std_logic

            );

END \K555LI6\;

ARCHITECTURE model OF \K555LI6\ IS

    BEGIN    

    \OUT1_-1\<= ( \IN1_-1\ AND \IN2_-1\ AND \IN3_-1\ AND \IN4_-1\ );

    \OUT1_-2\<= ( \IN1_-2\ AND \IN2_-2\ AND \IN3_-2\ AND \IN4_-2\ );   

END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \K555LE7\ IS

PORT(

            \IN1_-1\ : IN std_logic;

            \IN2_-1\ : IN std_logic;

            \IN3_-1\ : IN std_logic;

            \IN4_-1\ : IN std_logic;

            \IN5_-1\ : IN std_logic;

            \OUT1_-1\ : OUT std_logic;

            VCC : IN std_logic;

            GND : IN std_logic;

            \IN1_-2\ : IN std_logic;

            \IN2_-2\ : IN std_logic;

            \IN3_-2\ : IN std_logic;

            \IN4_-2\ : IN std_logic;

            \IN5_-2\ : IN std_logic;

            \OUT1_-2\ : OUT std_logic

);

END \K555LE7\;

ARCHITECTURE model OF \K555LE7\ IS

    BEGIN

    \OUT1_-1\<= NOT ( \IN1_-1\ OR \IN2_-1\ OR \IN3_-1\ OR \IN4_-1\ OR \IN5_-1\) after 17NS;

    \OUT1_-2\<= NOT ( \IN1_-2\ OR \IN2_-2\ OR \IN3_-2\ OR \IN4_-2\ OR \IN5_-2\) after 17NS;

END model;                

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \K555LA12\ IS PORT(

            \IN1_-1\ : IN std_logic;

            \IN2_-1\ : IN std_logic;

            \OUT1_-1\ : OUT std_logic;

            VCC : IN std_logic;

            GND : IN std_logic;

            \IN1_-2\ : IN std_logic;

            \IN2_-2\ : IN std_logic;

            \OUT1_-2\ : OUT std_logic;

            \IN1_-3\ : IN std_logic;

            \IN2_-3\ : IN std_logic;

            \OUT1_-3\ : OUT std_logic;

            \IN1_-4\ : IN std_logic;

            \IN2_-4\ : IN std_logic;

            \OUT1_-4\ : OUT std_logic

); END \K555LA12\;

ARCHITECTURE model OF \K555LA12\ IS

    BEGIN

    \OUT1_-1\ <= NOT ( \IN1_-1\ AND \IN2_-1\ );

    \OUT1_-2\ <= NOT ( \IN1_-2\ AND \IN2_-2\ );

    \OUT1_-3\ <= NOT ( \IN1_-3\ AND \IN2_-3\ );