Создание структурных и поведенческих моделей исследуемого цифрового узла (элемент К555IM6 (двоичный 4-разрядный сумматор)) в пакетах DesignLab 8, OrCad 9.1, страница 2

7.3. Текстовое SPICE-описание моделируемого узла

Содержимое файла ver1.cir:

* D:\IM6\DL8\ver1.sch

* Schematics Version 8.0 - July 1997

* Sun Nov 27 18:37:28 2005

** Analysis setup **

.tran 20ns 1000ns

.OPTIONS DIGMNTYMX=3

.LIB "D:\IM6\DL8\my_lib.lib"                                 личная библиотека

.STMLIB "D:\IM6\DL8\ver.stl"                                файл описания внешних воздействий

* From [SCHEMATICS NETLIST] section of msim.ini:

.lib "nom.lib"

.INC "ver1.net"

.INC "ver1.als"

.probe

.END

Рис 9. Файл ver1.cir

Содержимое файлаver1.net:

* Schematics Netlist *

U_DSTM3         STIM(1,0) $G_DPWR $G_DGND HS1_CI IO_STM STIMULUS=CI

U_DSTM2         STIM(4,0) $G_DPWR $G_DGND HS1_A3 HS1_A2 HS1_A1 HS1_A0 IO_STM

+  STIMULUS=A

U_DSTM1         STIM(4,0) $G_DPWR $G_DGND HS1_B3 HS1_B2 HS1_B1 HS1_B0 IO_STM

+  STIMULUS=B

X_HS1_DD1_1         HS1_A1 HS1_B1 HS1_U1 $G_DPWR $G_DGND K555LE1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD1_2         HS1_A2 HS1_B2 HS1_U2 $G_DPWR $G_DGND K555LE1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD1_3         HS1_A3 HS1_B3 HS1_U3 $G_DPWR $G_DGND K555LE1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD2_1         HS1_CI HS1_UC $G_DPWR $G_DGND K555LN1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD1_4         HS1_A0 HS1_B0 HS1_U0 $G_DPWR $G_DGND K555LE1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD3_1         HS1_A0 HS1_B0 HS1_Y0 $G_DPWR $G_DGND K555LA12 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD3_2         HS1_A1 HS1_B1 HS1_Y1 $G_DPWR $G_DGND K555LA12 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD3_3         HS1_A2 HS1_B2 HS1_Y2 $G_DPWR $G_DGND K555LA12 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD3_4         HS1_A3 HS1_B3 HS1_Y3 $G_DPWR $G_DGND K555LA12 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD4_1         $N_0001 $N_0002 HS1_S0 $G_DPWR $G_DGND K555LP5 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD2_2         HS1_UC $N_0001 $G_DPWR $G_DGND K555LN1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD5_1         $N_0003 HS1_Y0 $N_0002 $G_DPWR $G_DGND K555LI1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD2_3         HS1_U0 $N_0003 $G_DPWR $G_DGND K555LN1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD5_2         HS1_Y0 HS1_UC $N_0004 $G_DPWR $G_DGND K555LI1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD6_1         HS1_U0 $N_0004 $N_0005 $G_DPWR $G_DGND K555LE1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD4_2         $N_0006 $N_0005 HS1_S1 $G_DPWR $G_DGND K555LP5 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD2_4         HS1_U1 $N_0007 $G_DPWR $G_DGND K555LN1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD5_3         HS1_Y1 $N_0007 $N_0006 $G_DPWR $G_DGND K555LI1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD4_3         $N_0008 $N_0009 HS1_S2 $G_DPWR $G_DGND K555LP5 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD5_4         HS1_U0 HS1_Y1 $N_0010 $G_DPWR $G_DGND K555LI1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD7_1         HS1_U1 $N_0010 $N_0011 $N_0009 $G_DPWR $G_DGND K555LE4

+  PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD8_1         HS1_Y1 HS1_Y0 HS1_UC $N_0011 $G_DPWR $G_DGND K555LI3

+  PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD2_5         HS1_U2 $N_0012 $G_DPWR $G_DGND K555LN1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD9_1         HS1_Y2 $N_0012 $N_0008 $G_DPWR $G_DGND K555LI1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD9_2         HS1_U1 HS1_Y2 $N_0013 $G_DPWR $G_DGND K555LI1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD8_2         HS1_Y1 HS1_Y2 HS1_U1 $N_0014 $G_DPWR $G_DGND K555LI3

+  PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD2_6         HS1_U3 $N_0015 $G_DPWR $G_DGND K555LN1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD9_3         HS1_Y3 $N_0015 $N_0016 $G_DPWR $G_DGND K555LI1 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_HS1_DD4_4         $N_0016 $N_0017 HS1_S3 $G_DPWR $G_DGND K555LP5 PARAMS: