Создание структурных и поведенческих моделей исследуемого цифрового узла (элемент К555IM6 (двоичный 4-разрядный сумматор)) в пакетах DesignLab 8, OrCad 9.1, страница 10

    \OUT1_-4\ <= NOT ( \IN1_-4\ AND \IN2_-4\ );

END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \K555LE4\ IS PORT(

            \IN1_-1\ : IN std_logic;

            \IN2_-1\ : IN std_logic;

            \IN3_-1\ : IN std_logic;

            \OUT1_-1\ : OUT std_logic;

            VCC : IN std_logic;

            GND : IN std_logic;

            \IN1_-2\ : IN std_logic;

            \IN2_-2\ : IN std_logic;

            \IN3_-2\ : IN std_logic;

            \OUT1_-2\ : OUT std_logic;

            \IN1_-3\ : IN std_logic;

            \IN2_-3\ : IN std_logic;

            \IN3_-3\ : IN std_logic;

            \OUT1_-3\ : OUT std_logic

); END \K555LE4\;

ARCHITECTURE model OF \K555LE4\ IS

    BEGIN

    \OUT1_-1\ <= NOT ( \IN1_-1\ OR \IN2_-1\ OR \IN3_-1\ );

    \OUT1_-2\ <= NOT ( \IN1_-2\ OR \IN2_-2\ OR \IN3_-2\ );

    \OUT1_-3\ <= NOT ( \IN1_-3\ OR \IN2_-3\ OR \IN3_-3\ );

END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \K555LI1\ IS PORT(

            \IN1_-1\ : IN std_logic;

            \IN2_-1\ : IN std_logic;

            \OUT1_-1\ : OUT std_logic;

            VCC : IN std_logic;

            GND : IN std_logic;

            \IN1_-2\ : IN std_logic;

            \IN2_-2\ : IN std_logic;

            \OUT1_-2\ : OUT std_logic;

            \IN1_-3\ : IN std_logic;

            \IN2_-3\ : IN std_logic;

            \OUT1_-3\ : OUT std_logic;

            \IN1_-4\ : IN std_logic;

            \IN2_-4\ : IN std_logic;

            \OUT1_-4\ : OUT std_logic

);END \K555LI1\;

ARCHITECTURE model OF \K555LI1\ IS

    BEGIN

    \OUT1_-1\ <=  ( \IN1_-1\ AND \IN2_-1\ );

    \OUT1_-2\ <=  ( \IN1_-2\ AND \IN2_-2\ );

    \OUT1_-3\ <=  ( \IN1_-3\ AND \IN2_-3\ );

    \OUT1_-4\ <=  ( \IN1_-4\ AND \IN2_-4\ );

END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \K555LI3\ IS PORT(

            \IN1_-1\ : IN std_logic;

            \IN2_-1\ : IN std_logic;

            \IN3_-1\ : IN std_logic;

            \OUT1_-1\ : OUT std_logic;

            VCC : IN std_logic;

            GND : IN std_logic;

            \IN1_-2\ : IN std_logic;

            \IN2_-2\ : IN std_logic;

            \IN3_-2\ : IN std_logic;

            \OUT1_-2\ : OUT std_logic;

            \IN1_-3\ : IN std_logic;

            \IN2_-3\ : IN std_logic;

            \IN3_-3\ : IN std_logic;

            \OUT1_-3\ : OUT std_logic

);END \K555LI3\;

ARCHITECTURE model OF \K555LI3\ IS

    BEGIN

    \OUT1_-1\ <=  ( \IN1_-1\ AND \IN2_-1\ AND \IN3_-1\ );

    \OUT1_-2\ <=  ( \IN1_-2\ AND \IN2_-2\ AND \IN3_-2\ );

    \OUT1_-3\ <=  ( \IN1_-3\ AND \IN2_-3\ AND \IN3_-3\ );

END model;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \K555LP5\ IS PORT(

            \IN1_-1\ : IN std_logic;

            \IN2_-1\ : IN std_logic;

            \OUT1_-1\ : OUT std_logic;

            VCC : IN std_logic;

            GND : IN std_logic;

            \IN1_-2\ : IN std_logic;

            \IN2_-2\ : IN std_logic;

            \OUT1_-2\ : OUT std_logic;

            \IN1_-3\ : IN std_logic;

            \IN2_-3\ : IN std_logic;

            \OUT1_-3\ : OUT std_logic;

            \IN1_-4\ : IN std_logic;

            \IN2_-4\ : IN std_logic;

            \OUT1_-4\ : OUT std_logic

);END \K555LP5\;

ARCHITECTURE model OF \K555LP5\ IS

    BEGIN

    \OUT1_-1\ <=  ( \IN1_-1\ XOR \IN2_-1\ ) AFTER 24 ns;

    \OUT1_-2\ <=  ( \IN1_-2\ XOR \IN2_-2\ ) AFTER 24 ns;

    \OUT1_-3\ <=  ( \IN1_-3\ XOR \IN2_-3\ ) AFTER 24 ns;

    \OUT1_-4\ <=  ( \IN1_-4\ XOR \IN2_-4\ ) AFTER 24 ns;

END model;